Tag: RISC-V

SiFive Freedom E310 processor

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

OpenPiton+Ariane Block Diagram

PULP, OpenPiton Partner on OpenPiton+Ariane Design

The OpenPiton project has announced a partnership with the PULP Platform to combine the OpenPiton open-source research processor platform with the 64-bit Ariane RISC-V core, creating what is described as “the ideal permissive open-source RISC-V system.” The Parallel Ultra Low Power (PULP) Platform announced Ariane, a 64-bit application-class RISC-V design,… Read More
OpenISA VEGAboard

OpenISA Launches New, Free RISC-V VEGAboard

OpenISA has officially launched the VEGAboard microcontroller development board, based on the PULP Platform’s RI5CY and Zero-RI5CY RISC-V core, and it’s giving them away to encourage adoption of the free instruction set architecture (ISA). Developed in partnership with the Parallel Ultra Low Power (PULP) Platform, Express Logic, Foundries.io, Ashling, IAR… Read More
SiFive HiFive Unleashed Board

SiFive, Nvidia Partner for RISC-V, NVDLA Edge AI SoC

RISC-V pioneer SiFive has announced a partnership with graphics and Arm-based processor giant Nvidia to integrate the former’s RISC-V core intellectual property with the latter’s deep-learning acceleration IP in a single high-performance system-on-chip (SoC) design. “Nvidia open sourced its NVDLA [Nvidia Deep Learning Architecture] architecture to drive the adoption of… Read More
Bluespec Piccolo Block Diagram

Bluespec Releases Apache-Licensed Piccolo RISC-V Core

Massachusetts-based Bluespec, a founding member of the RISC-V Foundation, has released the first entry in its open-source RISC-V processor family: the 32-bit three-stage Piccolo. Designed, the company explains, for Internet of Things (IoT) and other embedded uses, the small-footprint Piccolo design uses the 32-bit RV32IM variant of the open RISC-V… Read More