Tag: RISC-V

SiFive Freedom E310 processor

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

PlatformIO Logo

Western Digital Partners with SiFive, PlatformIO for Extended Open-Source Dev Toolset

Western Digital has announced a partnership with SiFive and PlatformIO Labs which will see the latter’s embedded development platform extended in order to provide a vendor-agnostic, end-to-end open environment with full RISC-V support. Western Digital’s interest in embedded development in general and the open RISC-V instruction set architecture (ISA) specifically… Read More
Gentoo Linux Logo

Gentoo Linux Announces Experimental RISC-V Support

The Gentoo Linux distribution has announced initial, experimental support for the free and open RISC-V instruction set architecture (ISA). “After some preparations, we’re happy to announce (initially experimental) support for a new arch: riscv,” writes Andreas Huettel in the gentoo-dev mailing list. “The keyword is ‘~riscv’; no stable keyword… Read More
QEMU Logo

QEMU 4.0.0 Brings New RISC-V Features

Version 4.0.0 of the QEMU emulator has been released, bringing with it new features for those working with the RISC-V instruction set architecture (ISA). Designed to allow a system to run code designed for a different instruction set, emulation via QEMU or a similar package is a key part of… Read More