The RISC-V Foundation has announced the formal ratification of the processor trace specification, introducing a standardised trace encoder algorithm for the free and open-source instruction set architecture as a means of assisting with debugging.

“RISC-V is rapidly gaining popularity due to its open and modular design that supports customisation on top of a standard core ISA,” says Krste Asanović, chair of the RISC-V Foundation Board of Directors. “The RISC-V ecosystem continues to showcase a large degree of interoperability among various vendors’ implementations.

“With the processor trace specification ratified, trace IP developers, SoC integration engineers, and debug software developers have agreed on a highly efficient compressed standard for representing program flow on a RISC-V core.”

“Understanding a system’s program behaviour is often quite difficult, especially when working with complex systems for the HPC, Internet of Things, machine learning and artificial intelligence,” adds Gajinder Panesar, chair of the RISC-V Foundation’s Trace and Debug Standing Committee. “Developers and engineers spend around 50-75 percent of their time debugging and integrating tools and extensions.

“With the processor trace specification ratified, users are able to choose core vendors and trace encoder suppliers knowing tools vendors will support this standard moving forward.”

The trace specification is available now on the RISC-V Foundation website, alongside the ISA specification and version 0.1 of the in-progress compliance framework.