The RISC-V Foundation has announced the agenda for its second annual RISC-V summit, taking place this December in San Jose, California.
“The RISC-V Foundation, in partnership with Informa’s Tech Division, is hosting its annual RISC-V Summit, a four-day conference featuring keynotes, smaller breakout sessions, tutorials, exhibitions and networking receptions, as well as member meetings to open the week’s events,” the Foundation explains. “Leading technology companies and research institutions will share notable product updates, projects and implementations and discuss how the RISC-V ISA is driving the next generation of hardware, software and IP. The keynotes for the RISC-V Summit will include representatives from Arm, IBM, Microchip, OpenHW Group, SiFive, and Western Digital.”
The event is, as with the RISC-V Summit 2018, split into closed and open sessions. The first day of the event, Monday the 9th of December, is open only to Foundation member companies; the Tuesday and Wednesday sessions are open to all with keynote speakers in the mornings and breakout sessions in the afternoon; finally, an open workshop day on the Thursday features technical tutorials and investigations into real-world RISC-V usage.
Confirmed speakers include RISC-V Foundation chief executive Calista Redmond, SiFive’s Krste Asanovic, Western Digital’s Martin Fink, Microchip’s Ted SPeers, SiFive’s Yunsup Lee, RISC-V Foundation vice-chair David Patterson, Red Hat’s Wei Fu, Embecosm’s Jeremy Bennet, NXP’s Joe Circello, and FreeRTOS’ Ricahrd Berry, as well as a talk by Google’s Richard Ho and Tao Lui on open-source verification for RISC-V processors.
The full schedule, including registration links, can be found on the event website.