Tag: RISCV

SiFive Freedom E310 processor

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

Microsemi PolarFire SoC Block Diagram

Microchip Open Early Access Programme for RISC-V-Enabled PolarFire SoC FPGA Family

Microchip has opened an early access programme for its RISC-V-enabled PolarFire SoC family of field-programmable gate arrays (FPGAs), providing what the company claims is “the world’s first hardened real-time Linux-capable RISC-V-based microprocessor subsystem” to a low-power FPGA range. “Delivering the industry’s first RISC-V based SoC FPGA along with our Mi-V… Read More
OpenHW Group Logo

OpenHW Group Unveils CORE-V Chassis SoC Project, Building on PULP Project IP

OpenHW Group has announced a project to create a heterogeneous multi-core processor evaluation system-on-chip (SoC) design, featuring a high-performance 64-bit core coupled with a lower-power 32-bit core: the CORE-V Chassis. “The CORE-V Chassis project will help validate that serious silicon development is possible utilising the ethos of open-source hardware, IP,… Read More
fentISS

Dependable Real-time Infrastructure for Safety-critical Computer (De-RISC) Aims for the Stars

Cobham Gaisler and fentISS have confirmed that the now-funded De-RISC project is forging ahead with its efforts to built a RISC-V based space-qualified computing platform centred in Europe, in partnership with Barcelona Supercomputing Centre and Thales. “With the first RISC-V based, fully European platform for space, De-RISC will guarantee access… Read More