SiFive Freedom E310 processor

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.


QEMU 4.1.0 Extends RISC-V Open ISA Support

The open-source QEMU machine emulator and virtualiser has received enhanced support for the open RISC-V instruction set architecture (ISA) in its 4.1.0 release. Following on from the 4.0.0 release back in April, QEMU 4.1.0 brings a range of improvements to its support for the open RISC-V ISA. Chief among… Read More
Andes Technology RISC-V Banner

Andes Technology Points to Explosive RISC-V Growth

Andes Technology has announced explosive demand for its proprietary processor cores based on the open RISC-V instruction set architecture (ISA), highlighting the growing demand for alternatives to x86, Arm, MIPS, and other proprietary ISAs. Born from the University of California at Berkeley in 2010, the open RISC-V instruction set architecture… Read More

Building a RISC-V PC

How we assembled a RISC-V desktop computer. (video at the bottom of this post.) While it’s clear that the most significant opportunities for RISC-V will be in democratising custom silicon for accelerating specific tasks and enabling new applications — and it’s already driving a renaissance in novel computer architectures, for… Read More