Alibaba has released the source code for its XuanTie E902, E906, C906, and C910 RISC-V processor cores, promising to follow their release with additional development tools, software development kits, and customisations in the future.
Designed by Alibaba’s T-Head semiconductor arm, the XuanTie C906 was launched as a low-power in-order core for the Internet of Things, finding a commercial home in Allwinner’s D1 system-on-chip. The C910 is a higher performance out-of-order design, still built with the Internet of Things in mind, which has so far only been announced in a limited-production-run developer’s kit. The two E-family cores, meanwhile, are simpler designs for more resource-constrained environments.
Now all four cores are available under the permissive Apache 2.0 licence, allowing anyone to download the source code and experiment, build, or modify it – and Alibaba promises that additional support, including software development kits for both cores, will follow.
“By opening up the IP cores of our in-house IoT processors as well as related software stacks and development tools, we aim to assist global developers to build their own RISC-V-based chips in a much more cost-effective way,” claims Jeff Zhang, president of Alibaba Cloud and head of the Alibaba DAMO Academy. “We hope this move can encourage more innovation among the thriving RISC-V software community, and as a result help people to enjoy the benefits of a connected world in the digital era.”
“Alibaba supports the RISC-V community through their continuous contributions, technical leadership, and deep collaboration with RISC-V stakeholders,” adds Calista Redmond, CEO of RISC-V International. “Alibaba leads by example and has inspired the global RISC-V community to increase innovation in chip development with benefits to the entire RISC-V ecosystem.”
Those interested in building on the cores, however, should be aware that they were created prior to the ratification of certain RISC-V standards – in particular the vector extensions. As a result, they are not technically fully compliant with the current RISC-V specification – and developers of the Linux kernel have already raised concerns about how the C906, in particular, will be supported in mainline.