Author: Gareth Halfacree

Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.

MIPI Launches Open Access to Nine Debug and Trace Specifications

The Mobile Industry Processor Interface (MIPI) Alliance has announced it is providing its debug and trace specifications, nine in total, under open access terms for the first time – including its latest SneakPeek Protocol v2.0. “Opening up access to MIPI debug and trace specifications will foster a more standardised debug… Read More

Antmicro Releases FastVDMA Open-Source Resource-Light DMA Controller

Antmicro has announced the release of FastVDMA, an open-source direct memory access (DMA) controller designed to improve the freedom of FPGA-based free and open source silicon projects. “One of the main motivations leading to the design of an open source DMA controller was the lack of portable open source alternatives… Read More

Calista Redmond Points to Growing Momentum for FOSSi, RISC-V

RISC-V Foundation chief executive officer Calista Redmond has written of increasing momentum for RISC-V, as the semiconductor industry begins to shift away from proprietary closed-source core. “Interest in RISC-V has been gaining steam with commercial implementations and adoption rapidly growing. It has been incredible to witness how RISC-V has fostered… Read More

FOSSi Foundation Details Google Summer of Code 2019 Project Wins

The Free and Open Source Silicon (FOSSi) Foundation has announced the end of its participation in the 2019 Google Summer of Code programme, with seven students contributing to projects under the Foundation’s umbrella mentorship. Run by Google each year as a means of matching students with mentors already in the… Read More

Nvidia Turns to RISC-V for RC18 Research Chip IO Core

High-performance computing company Nvidia has detailed another of its products to use the open RISC-V instruction set architecture (ISA), this time as an input/output core in an inference accelerator part it calls RC18. Developed by the company last year and unveiled in detail during the Hot Chips conference, RC18 is… Read More

Tasmania Gets State-Wide LoRaWAN Network for IoT Development

Internet of Things (IoT) specialist Definium Technologies has announced the activation of a state-wide LoRaWAN network in its native Tasmania, aiming to make the region an ideal test-bed for IoT solutions. “We decided to take on the challenge of rolling out a statewide enterprise-grade LoRaWAN network,” explains Mike Cruse, chief… Read More

MIT Unveils World’s First RISC-V Carbon Nanotube Processor, RV16XNano

Researchers from the Massachusetts Institute of Technology (MIT), working with Analog Devices, have announced the production and execution of the world’s first 16-bit programmable processor built around carbon nanotube field-effect transistors (CNFETs) – and they’ve implemented the open RISC-V instruction set architecture (ISA) on it. One of a range of… Read More

DARPA Takes RISC-V SSITH Voting Machine Prototype to DEF CON 2019

The US Defence Advanced Research Projects Agency (DARPA) has unveiled the first prototype of its System Security Integrated Through Hardware and Firmware (SSITH) platform for future electronic voting machines, based on an in-house RISC-V processor. Announced back in 2017, the SSITH programme sees researchers working on securing future computing systems… Read More

CRU: LoRaWAN World Records, SweRVolf SoC, OpenPower, and More

The Things Network, the community-driven LoRaWAN project, has announced a world record successful transmission distance from the Servet project: 476 miles, or 766 kilometres. Designed for low power yet wide area use, LoRaWAN is the technology behind community-driven wide-area networking project The Things Network – the largest open LoRaWAN network… Read More

GigaDevice Unveils Low-Cost GD32V RISC-V Microcontroller

GigaDevice, a company which has previously concentrated on microcontrollers built around the proprietary Arm instruction set architecture (ISA), has released a new part based on the open RISC-V ISA: GD32V. First spotted by RISC-V pioneer Sipeed late yesterday, the GigaDevice GD32V is based on the Nucleisys N20x RISC-V core,… Read More

IBM, OpenPOWER Foundation Make POWER ISA Open At Last

IBM’s OpenPOWER Foundation, set up to build the POWER architecture ecosystem, has made a milestone announcement: it is to make the POWER instruction set architecture, along with key hardware designs and supporting technologies, available under an open source licence. Announced along with the news that the OpenPOWER Foundation is to… Read More

QEMU 4.1.0 Extends RISC-V Open ISA Support

The open-source QEMU machine emulator and virtualiser has received enhanced support for the open RISC-V instruction set architecture (ISA) in its 4.1.0 release. Following on from the 4.0.0 release back in April, QEMU 4.1.0 brings a range of improvements to its support for the open RISC-V ISA. Chief among… Read More