Wavious, a fabless semiconductor company which offers a platform based on mix-and-match “chiplets,” has launched a RISC-V-powered open-source LPDDR4x/5 PHY – under the permissive Apache 2.0 licence.
“We are strong believers in open-source hardware and software,” the company said in its announcement, “and Wavious is dedicated to making significant contributions to the open source community. Open-source HW [hardware] and chiplets are both necessary to remove barriers to entry and to drive innovation in system design.”
The IP, which includes the physical interface hardware and supporting software, is capable of driving LPDDR4x memory at 4,266Gb/s and newer LPDDR5 memory at 6,400Gb/s. It includes dual-rank support, a DFI 5.0-compliant memory controller interface, per-bit deskew, and embedded phase-linked loop (PLL), calibration logic, and training buffer.
It also leans on a very well known open silicon project: RISC-V, integrating a microcontroller unit based on the free and open-source instruction set architecture alongside embedded static RAM (SRAM).
While the IP itself is permissively licensed, however, it relies on the proprietary Cadence Simulation Verification IP (VIP) toolchain for full verification testing. For those without access, the company has provided two basic tests: a boot test for the microcontroller unit, running at 422MHz; and a DDR loopback test running at 2,112MHz.
“The WDDR PHY IP has been taped-out in the WLP120 chiplet,” the company confirmed, “as part of the Wavious Chiplet Platform ecosystem.”
Wavious has published the code under the permissive Apache 2.0 licence on GitHub, across two repositories: one for the hardware PHY and one for the software, which is based on FreeRTOS.