Tag: RISCV

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

BSC Opens the European Laboratory for Open Computer Architecture, LOCA

The Barcelona Supercomputer Centre (BSC) has announced the opening of the European Laboratory for Open Computer Architecture (LOCA), which aims to develop both energy-efficient and high-performance chips based on open instruction set architectures (ISAs). “LOCA will be a collaborative laboratory that welcomes companies, foundations and academic institutions that share the… Read More

Observer Tacks RISC-V Cores to Sensors to Simplify Heterogeneous Aggregation

Olof Kindgren, director of the Free and Open Source Silicon Foundation (FOSSi Foundation), has released a tool designed to make multi-sensor aggregation on field-programmable gate arrays (FPGAs) simpler: the RISC-V-powered Observer. “Implementing the logic for sensor communication, post processing and format conversion directly in an FPGA can quickly become very… Read More

RISC-V Hits the Browser Courtesy of Martin Strubel’s CI Docker Image

Martin Strubel has released a guide to running a RISC-V core directly in a browser – though admits that it’s unsurprisingly not quite as performant as if it were running in a native emulator or on dedicated hardware. “I though I’d share some open source approach to let a RISC-V… Read More

FOSDEM 2020 RISC-V Devroom Opens Call for Participation

The organisers of the RISC-V Devroom at the FOSDEM 2020 conference, taking place in Brussels this coming February, have opened the call for talk proposals. “FOSDEM 2020 will take place on February 1-2, 2020 in Brussels, Belgium. There will be a half day RISC-V developer’s room on February 1st (Saturday),”… Read More

RISC-V Foundation Announces Security-Focused Soft-Core CPU Contest Winners

The RISC-V Foundation has announced the winners of its RISC-V Soft CPU Contest, launched back in July with a view to promoting security-focused RISC-V implementations. “With the proliferation of connected devices, security is one of the key challenges in hardware design. The free and open RISC-V ISA presents an… Read More

CRU: RISC-V Momentum, Carbon Nanotubes, Fire, ICE, and More

RISC-V Foundation chief executive officer Calista Redmond has written of increasing momentum for RISC-V, as the semiconductor industry begins to shift away from proprietary closed-source core. “Interest in RISC-V has been gaining steam with commercial implementations and adoption rapidly growing. It has been incredible to witness how RISC-V has fostered… Read More

Calista Redmond Points to Growing Momentum for FOSSi, RISC-V

Nvidia Turns to RISC-V for RC18 Research Chip IO Core

High-performance computing company Nvidia has detailed another of its products to use the open RISC-V instruction set architecture (ISA), this time as an input/output core in an inference accelerator part it calls RC18. Developed by the company last year and unveiled in detail during the Hot Chips conference, RC18 is… Read More

MIT Unveils World’s First RISC-V Carbon Nanotube Processor, RV16XNano

Researchers from the Massachusetts Institute of Technology (MIT), working with Analog Devices, have announced the production and execution of the world’s first 16-bit programmable processor built around carbon nanotube field-effect transistors (CNFETs) – and they’ve implemented the open RISC-V instruction set architecture (ISA) on it. One of a range of… Read More

DARPA Takes RISC-V SSITH Voting Machine Prototype to DEF CON 2019

The US Defence Advanced Research Projects Agency (DARPA) has unveiled the first prototype of its System Security Integrated Through Hardware and Firmware (SSITH) platform for future electronic voting machines, based on an in-house RISC-V processor. Announced back in 2017, the SSITH programme sees researchers working on securing future computing systems… Read More

CRU: LoRaWAN World Records, SweRVolf SoC, OpenPower, and More

The Things Network, the community-driven LoRaWAN project, has announced a world record successful transmission distance from the Servet project: 476 miles, or 766 kilometres. Designed for low power yet wide area use, LoRaWAN is the technology behind community-driven wide-area networking project The Things Network – the largest open LoRaWAN network… Read More

GigaDevice Unveils Low-Cost GD32V RISC-V Microcontroller

GigaDevice, a company which has previously concentrated on microcontrollers built around the proprietary Arm instruction set architecture (ISA), has released a new part based on the open RISC-V ISA: GD32V. First spotted by RISC-V pioneer Sipeed late yesterday, the GigaDevice GD32V is based on the Nucleisys N20x RISC-V core,… Read More