The RISC-V Foundation has announced the winners of its RISC-V Soft CPU Contest, launched back in July with a view to promoting security-focused RISC-V implementations.
“With the proliferation of connected devices, security is one of the key challenges in hardware design. The free and open RISC-V ISA presents an incredible opportunity for the ecosystem to collaborate to develop more robust solutions for the growing security demands of today and the future,” said RISC-V Foundation chief executive Calista Redmond at the opening of the contest. “This contest is an opportunity for designers and hardware enthusiasts to rethink what is possible with computing design and build a secure RISC-V soft CPU that can prevent software security attacks.”
Now, the Foundation has announced the winners – and taking the top prize of €5,000 plus a HiFive Unleashed with Expansion Board add-on is Changyi Gu, whose Rattlesnake soft core scored 78 out of a possible 100 on the judging metrics while implementing a “dirty bit” protective system to tag consecutive suspicious writes and halts if tagged memory is executed.
The second-place prize went to Matthew Ballance for Featherweight RISC-V (FWRISC-S), which protects defined memory areas until the core is reset. Finally, third place went to Jörg Mische for RudolV, which also allows for memory regions to be defined as non-executable when associated with suspicious memory writes.
A special mention was also given to Ecco, a team made up of Alexey Baturo, Anatoly Parshintsev, Fedor Veselovsky, Igor Chervatyuk and Sergey Matveev, who presented a soft-core processor which implements memory tagging using a pseudorandom number generation. “Starting from the SPU32 processor, they showcased how RISC-V can enable anyone to work at a hardware level, even a team made up of software engineers,” the Foundation explains. “While the Ecco team’s solution ran on a different board than outlined by the contest rules (and was thus ineligible to win), we appreciate all their hard work.”