RISC-V Foundation chief executive officer Calista Redmond has written of increasing momentum for RISC-V, as the semiconductor industry begins to shift away from proprietary closed-source core.
“Interest in RISC-V has been gaining steam with commercial implementations and adoption rapidly growing. It has been incredible to witness how RISC-V has fostered industry-wide collaboration to solve tomorrow’s design needs, including some of the toughest challenges like security,” Redmond writes in an update on the Foundation’s progress. “Here’s why RISC-V is changing the face of the silicon industry.
“The RISC-V ISA allows us to start with a clean sheet of paper and optimize designs for new workloads, ushering in a new era of silicon design and processor innovation through open standard collaboration. This open source approach to silicon has many benefits.
“We’ve seen that RISC-V: 1) Unlocks architecture and enables innovation since RISC-V is a layered and extensible ISA, companies can easily implement the minimal instruction set, well defined extensions and custom extensions to create custom processors for these new and innovative workloads. 2) Reduces risk and investment via leverage of established and common IP building blocks with a growing set of shared tools and development resources with an engaged development community. 3) Creates opportunities to create thousands of possible custom processors as implementation is not defined at the ISA level, but rather by the composition of the SoC and other design attributes. It’s possible to go big, small, powerful, or lightweight. 4) Accelerates time to market through collaboration and open source IP reuse, this not only reduces development expense, but accelerates time to market.”
Redmond’s comments come at a time when the RISC-V Foundation has grown to over 325 members in 28 countries and an increasing number of commercial products featuring RISC-V cores, from human-machine interface devices and solid-state drives to AI accelerators, are reaching the market; it also comes as RISC-V faces increasing pressure from rival free and open source silicon projects, most notably the recently-opened Power instruction set architecture.
Redmond’s full post is available on the RISC-V Foundation blog.
Researchers from the Massachusetts Institute of Technology (MIT), working with Analog Devices, have announced the production and execution of the world’s first 16-bit programmable processor built around carbon nanotube field-effect transistors (CNFETs) – and they’ve implemented the open RISC-V instruction set architecture (ISA) on it.
One of a range of materials under investigation for the post-silicon era of semiconductors, in order to keep up with the observation turned target by Intel co-founder Gordon Moore that the number of transistors on a leading-edge part trends towards a doubling every 18 months, carbon nanotube transistors (CNTs) have the potential to operate with considerably higher efficiency than their silicon counterparts. The only problem: a high defect rate in production, meaning that previous cutting-edge CNT processors have been limited to fewer than 150 transistors per prototype.
A team of researchers at MIT, working under Professor Max M. Shulaker, have now made a breakthrough: DREAM, Designing Resiliency Against Metallic CNTs, a technology which has allowed them to produce a 16-bit CNFET processor with 14,000 transistors and implementing the open RISC-V instruction set architecture.
“This is by far the most advanced chip made from any emerging nanotechnology that is promising for high-performance and energy-efficient computing,” says Professor Shulaker of RV16XNano, which has been produced in prototype form and is already executing its first programs. “There are limits to silicon. If we want to continue to have gains in computing, carbon nanotubes represent one of the most promising ways to overcome those limits. [This paper] completely re-invents how we build chips with carbon nanotubes.”
Full details on the team’s work, which marks both the first 16-bit programmable carbon nanotube processor and the first carbon nanotube chip to be based on the research-friendly open RISC-V ISA, can be found in the journal Nature.
High-performance computing company Nvidia has detailed another of its products to use the open RISC-V instruction set architecture (ISA), this time as an input/output core in an inference accelerator part it calls RC18.
Developed by the company last year and unveiled in detail during the Hot Chips conference, RC18 is a high-performance accelerator for deep-learning inference workloads boasting 128 trillion operations per second in an energy-efficient 13.5W design. It is build around 16 processor elements (PEs), which have eight vector multiply accumulate (MAC) units each. While these are proprietary, input output and serial functionality is handled by a single master core – built on the RISC-V instruction set architecture.
While RC18 is a research chip, Nvidia is confident it could add the technology to a shipping product at any time. “The important thing is that we’ve demonstrated that anytime we want we can plop that into products,” Nvidia’s Bill Dally claims in an interview with Next Platform. “In fact, it can replace the Nvidia Deep Learning Accelerator. It’s actually designed very similarly to NVDLA, but we are as interested in the tools as much as we are about the chip. We developed the design space, exploration tools that try all combinations of vector widths, the number of vector units, the sizes of buffer arrays, and ways of tiling the loop to stage things. The tools came up with the optimal points for various neural networks.”
RC18 isn’t the first time Nvidia has turned to the RISC-V ISA: The company began shifting control cores in its graphics processing products away from proprietary ISAs several years ago, with RC18 simply the latest in a string of designs which take advantage of the open ISA’s accessibility, flexibility, and royalty-free status.
The US Defence Advanced Research Projects Agency (DARPA) has unveiled the first prototype of its System Security Integrated Through Hardware and Firmware (SSITH) platform for future electronic voting machines, based on an in-house RISC-V processor.
Announced back in 2017, the SSITH programme sees researchers working on securing future computing systems against attack with novel hardware and software, in particular new processor designs based on the open RISC-V instruction set architecture (ISA) but with SSITH-specific security features added. The core of the design is to produce a secure electronic voting machine – a goal which, in our opinion, is likely unachievable, though a more secure electronic voting machine than the proprietary systems currently available shouldn’t be too much of a challenge.
The first fruit of the project is a prototype device, based on a 64-bit RISC-V core running FreeBSD, which has been taken to the DEF CON 2019 hacker convention. “At this year’s Voting Village, hackers may find issues with the processors and quite frankly we would consider that a success,” explains Dr. Linton Salmon, programme manager for SSITH. “We want to be transparent about the technologies we are creating and find any problems in these venues before the technology is placed in another venue where a compromise could be more dangerous.”
Search Security reports that SSITH currently has 15 different RISC-V based prototypes in development, including the 64-bit variant on show at DEF CON, ranging from low-power embedded chips through to high-performance computing (HPC). Ruslan Bukin, meanwhile, has a shot of the prototype itself, running on a Xilinx FPGA development board, and claims that “soon all the voting machines in [the] U.S. will be powered by FreeBSD/RISC-V.”
More information on the SSITH programme itself is available on the DARPA website.
The Free and Open Source Silicon (FOSSi) Foundation has announced the end of its participation in the 2019 Google Summer of Code programme, with seven students contributing to projects under the Foundation’s umbrella mentorship.
Run by Google each year as a means of matching students with mentors already in the industry, the Google Summer of Code 2019 saw the FOSSi Foundation act as an umbrella organisation pairing students interested in the free and open source silicon movement with mentors on a range of projects. With autumn closing in, the Google Summer of Code is complete – and the Foundation has published the results of each student’s efforts.
“We at FOSSi Foundation are happy to announce that all of our Google Summer of Code (GSoC) students this year successfully completed their projects,” says director Philipp Wagner in the final GSoC update for 2019. “For multiple years now, FOSSi Foundation acted as umbrella organization for multiple GSoC projects. All projects were mentored by trusted community members, and we’re extremely happy how well the projects went! We owe a big thank you to all students and mentors, thanks to you, the free and open source hardware ecosystem is in a better place than before.”
Projects completed under GSoC 2019 include work on the 1st CLaaS framework for hardware acceleration of web applications and microservices, the integration of the WARP-V RISC-V core generator with the Chisel-based RocketChip system-on-chip (SoC) which led to a significant clock-speed improvement, the addition of a notification system to the LibreCores website, improvements to the LibreCores continuous integration (CI) coverage, the integration of the open ao486 soft core into the JuxtaPiton heterogeneous research processor, work on improving LLVM to support the development of a RISC-V-based general-purpose graphics processing unit (GPGPU), and improvements to the Ariane RISC-V microarchitecture.
Full details of each project, along with the names of students responsible for each and their mentors, can be found on the FOSSi Foundation website.
Antmicro has announced the release of FastVDMA, an open-source direct memory access (DMA) controller designed to improve the freedom of FPGA-based free and open source silicon projects.
“One of the main motivations leading to the design of an open source DMA controller was the lack of portable open source alternatives to proprietary controllers provided by FPGA vendors,” the company explains in its announcement. “This situation leads to a reduction in the reusability of DMA-based designs into different contexts when adopting multiple kinds of platforms, since DMA solutions tend to be tightly integrated with vendor-specific toolchains and IP. As a result, a non-negligible part of the work required in creating designs that implement proprietary DMA controllers, ends being highly platform-dependent and less useful to developers using other platforms.
“At Antmicro, we strongly advocate cross-platform and reproducible solutions to our customers, and are often the first to identify both immediate and long-term vendor lock-in constraints. The integration of FastVDMA with a portable SoC, such as LiteX, would solve the portability and platform-dependence of any DMA-based designs, and so allow for more engineering freedom in our FPGA projects.”
Antmicro’s solution, FastVDMA, supports multiple bus types – AXI4, AXI-Stream, and Wishbone – as write or read front-ends, supporting memory-to-memory, memory-to-stream, and stream-to-memory transfers without loading the CPU. Designed using the Chisel hardware design language, FastVDMA is claimed to be designed for minimal resource utilisation in order to make it as portable as possible which having been verified on hardware at 750MB/s for a 250MHz clock and 330MB/s at a 100MHz clock.
The Mobile Industry Processor Interface (MIPI) Alliance has announced it is providing its debug and trace specifications, nine in total, under open access terms for the first time – including its latest SneakPeek Protocol v2.0.
“Opening up access to MIPI debug and trace specifications will foster a more standardised debug environment, improving development processes and quality in and beyond the mobile device industry,” claims Joel Huloux, chair of MIPI Alliance, of his organisation’s surprise announcement this week. “In addition to allowing more developers to use the specifications, this step will strengthen the ecosystem, leading to broader interoperability and a richer development environment.”
The nine specifications now available to the public are: MIPI System Software-Trace, specifying a universal data format for the transmission of debug and trace information; MIPI Narrow Interface for Debug and Test, a specification which allows for debug and testing via functional ports on finished devices; the MIPI System Trace Protocol, a base protocol for application-specific trace functions; MIPI High-Speed Trace Interface and the related MIPI Parallel Trace Interface, for the exportation of trace data; MIPI Gigabit Debug for USB and MIPI Gigabit Debug for IP Sockets; and the new MIPI SneakPeek Protocol v.20, a standard communications protocol for debug and test applications and which includes MIPI TinySPP for low-bandwidth or high-latency interfaces.
“The IoT explosion is creating demand for millions of small, low-powered devices, such as sensors, in mobile and mobile-influenced systems,” adds Enrico Carrieri, chair of the MIPI Debug Working Group and Principal Engineer in Debug Architecture with Intel Corporation. “With MIPI SPP v2.0, TinySPP extends SneakPeek so it can be used for efficient debugging of these devices.”
All the standards are available for download now on the MIPI website.
IBM has made good on its commitment, through the OpenPOWER Foundation, to release an Open Memory Interface (OMI) under a permissive licence, with the first reference designs for its Fire OMI host and ICE two-port DDR4 OMI device hitting GitHub this month.
The OpenPOWER Foundation made the surprising announcement that it was shifting the POWER instruction set architecture (ISA) to an an open model back in August, partnering with the Linux Foundation to release POWER under a permissive licence. At the time, the Foundation also pledged to release reference designs for OpenCAPI and the Open Memory Interface – which are now available for the first time.
IBM’s releases, announced by DARPA’s Andreas Olofsson, take two forms. The first is ICE, a reference design for an Open Memory Interface device offering two DDR4 memory ports. The second is Fire, an example host designed for testing an OMI device – including, naturally, ICE.
In both cases, the files have been made available through the OpenCAPI Consortium under the permissive Apache Licence 2.0, including Verilog and VHDL sources. Both are available to download now from the ICE and Fire GitHub repositories, while FOSSi Foundation director Olof Kindgren has suggested they are suitable for FuseSoC packaging.
Linus Torvalds has officially launched Linux 5.3, the latest release of the popular open-source kernel, and it brings with it a range of improvements and new features for the RISC-V instruction set architecture (ISA).
“So we’ve had a fairly quiet last week, but I think it was good that we ended up having that extra week and the final rc8 [release candidate 8],” Torvalds writes in the release announcement. “Even if the reason for that extra week was my travel schedule rather than any pending issues, we ended up having a few good fixes come in, including some for some bad btrfs behaviour. Yeah, there’s some unnecessary noise in there too (like the spelling fixes), but we also had several last-minute reverts for things that caused issues.”
CNX Software has pulled out the changes of biggest interest to embedded developers, including those working with the free and open RISC-V instruction set architecture. These include image-header support for RISC-V kernel binaries, designed to be compatible with ARM64 image headers, a two-stage initial page table setup process, support for CONFIG_SOC starting with SiFive’s range of RISC-V systems-on-chips, DT data for the SiFive FU540 and HiFive Unleashed’s gigabit Ethernet controller, support for PCI Express message-signalled interrupts, and support for the new clone3 RV64 syscall.
Additional RISC-V-related changes include the addition of a new maintainer, Paul Walmsley, and a switch to a new shared RISC-V git tree – and, interestingly, a fix for an issue in the get_maintainers.pl script which was triggered for patches involving SiFive email addresses.
Linux 5.3, as with all Linux releases, is available now from the Linux kernel archive site.
Finally, Internet of Things (IoT) specialist Definium Technologies has announced the activation of a state-wide LoRaWAN network in its native Tasmania, aiming to make the region an ideal test-bed for IoT solutions.
“We decided to take on the challenge of rolling out a statewide enterprise-grade LoRaWAN network,” explains Mike Cruse, chief executive of Definium Technologies, at the launch. “We want to encourage people to come to Tasmania and test their IoT solutions, then deploy them around the state with enterprise-grade reliability. Tasmania is the ideal life-sized laboratory at scale where individuals and businesses of all scales can experiment with next-generation IoT applications, such as applying intelligent sensors to asset management, agricultural, horticultural, and aquaculture use cases.”
“The increasing deployment of large scale LoRaWAN networks using Semtech’s LoRa devices reflects a trend toward the growing adoption of IoT globally,” adds Marc Pegulu, vice president of IoT for Semtech’s Wireless and Sensing Products Group which is behind the LoRa and LoRaWAN standard and protocol. “Definium’s deployment in Tasmania will expose businesses, students and potential developers to IoT, and is expected to bring thousands of devices online to enable smarter solutions in a variety of vertical markets.”
The launch of the network comes shortly after Semtech opened its educational LoRaWAN Academy resources to all and community-driven LoRaWAN network initiative The Things Network set a new world record for transmission distance.