Martin Strubel has released a guide to running a RISC-V core directly in a browser – though admits that it’s unsurprisingly not quite as performant as if it were running in a native emulator or on dedicated hardware.
“I though I’d share some open source approach to let a RISC-V spin in the cloud – a few 1000 times slower than reality, but still fast enough to run the ISA tests and – for fun – to talk to the SoC through a virtual UART,” Strubel writes in a post to the RISC-V hardware developers’ mailing list. “Thanks to the docker community, this can all run in the browser without having to install a lot of software (let aside resolving dependencies).
“The other good thing is that this integrates nicely into GitHub so that when breaking stuff during development, this will show. The actual engine behind it is the open source GHDL simulator. So the entire thing is pretty VHDL specific, however with a bit of work this could also done with licence-free Verilog simulators – which would be nice to have someday, to do synthesis the ‘open source continuous integration’ way as well (with Yosys).”
Designed primarily for continuous integration (CI), instructions on getting Strubel’s Docker image up and running for in-browser RISC-V experimentation can be found on the Section 5 website.