The US Defence Advanced Research Projects Agency (DARPA) has unveiled the first prototype of its System Security Integrated Through Hardware and Firmware (SSITH) platform for future electronic voting machines, based on an in-house RISC-V processor.
Announced back in 2017, the SSITH programme sees researchers working on securing future computing systems against attack with novel hardware and software, in particular new processor designs based on the open RISC-V instruction set architecture (ISA) but with SSITH-specific security features added. The core of the design is to produce a secure electronic voting machine – a goal which, in our opinion, is likely unachievable, though a more secure electronic voting machine than the proprietary systems currently available shouldn’t be too much of a challenge.
The first fruit of the project is a prototype device, based on a 64-bit RISC-V core running FreeBSD, which has been taken to the DEF CON 2019 hacker convention. “At this year’s Voting Village, hackers may find issues with the processors and quite frankly we would consider that a success,” explains Dr. Linton Salmon, programme manager for SSITH. “We want to be transparent about the technologies we are creating and find any problems in these venues before the technology is placed in another venue where a compromise could be more dangerous.”
Search Security reports that SSITH currently has 15 different RISC-V based prototypes in development, including the 64-bit variant on show at DEF CON, ranging from low-power embedded chips through to high-performance computing (HPC). Ruslan Bukin, meanwhile, has a shot of the prototype itself, running on a Xilinx FPGA development board, and claims that “soon all the voting machines in [the] U.S. will be powered by FreeBSD/RISC-V.”
More information on the SSITH programme itself is available on the DARPA website.