High-performance computing company Nvidia has detailed another of its products to use the open RISC-V instruction set architecture (ISA), this time as an input/output core in an inference accelerator part it calls RC18.

Developed by the company last year and unveiled in detail during the Hot Chips conference, RC18 is a high-performance accelerator for deep-learning inference workloads boasting 128 trillion operations per second in an energy-efficient 13.5W design. It is build around 16 processor elements (PEs), which have eight vector multiply accumulate (MAC) units each. While these are proprietary, input output and serial functionality is handled by a single master core – built on the RISC-V instruction set architecture.

While RC18 is a research chip, Nvidia is confident it could add the technology to a shipping product at any time. “The important thing is that we’ve demonstrated that anytime we want we can plop that into products,” Nvidia’s Bill Dally claims in an interview with Next Platform. “In fact, it can replace the Nvidia Deep Learning Accelerator. It’s actually designed very similarly to NVDLA, but we are as interested in the tools as much as we are about the chip. We developed the design space, exploration tools that try all combinations of vector widths, the number of vector units, the sizes of buffer arrays, and ways of tiling the loop to stage things. The tools came up with the optimal points for various neural networks.”

RC18 isn’t the first time Nvidia has turned to the RISC-V ISA: The company began shifting control cores in its graphics processing products away from proprietary ISAs several years ago, with RC18 simply the latest in a string of designs which take advantage of the open ISA’s accessibility, flexibility, and royalty-free status.