Think Silicon has announced the development of a general-purpose graphics processor (GPGPU) with 3D acceleration capabilities built on the free and open RISC-V instruction set architecture (ISA) – and claims it will be the first in the industry to demonstrate such a device working, at the RISC-V Summit later this month.
“Building a GPGPU on RISC-V instruction set architecture is another significant milestone in the young history of Think Silicon,” says Think Silicon’s senior vice president for sales and marketing Ulli Mueller of the company’s decision to adopt the ISA. “With the announcement of NEOX|V, we’re delivering the essential low-power GPU technologies to enable companies to create efficient and nimble solutions for a wide variety of markets.”
“The elegance and simplicity of the RISC-V ISA used in NEOX|V will enable a new class of SoCs,” adds chief technology officer Iakovos Stamoulis, “which are smaller, consume less energy and are easier and more open to program.”
The company is hoping that developers will look towards RISC-V for both central (CPU) and graphics (GPU) processing in low-power embedded systems, talking of a new approach to programming which would allow a system to switch a workload between CPU and GPU seamlessly – in contrast to current GPUs, which use a very different architecture to CPUs and can only run specially-constructed code.
Think Silicon has not yet announced commercial availability of the NEOX|V family, but has confirmed it will be demonstrating it at the RISC-V Summit in California between the 10th and 12th of December 2019.