OpenHW Group has announced a project to create a heterogeneous multi-core processor evaluation system-on-chip (SoC) design, featuring a high-performance 64-bit core coupled with a lower-power 32-bit core: the CORE-V Chassis.

“The CORE-V Chassis project will help validate that serious silicon development is possible utilising the ethos of open-source hardware, IP, and tools,” claims OpenHW Group president and chief executive Rick O’Connor. “With the tape out of a functional evaluation SoC during the second half of 2020, we will demonstrate that the open hardware mindset is as capable and dependable as any of today’s closed-source alternatives.”

The design in question is based on the NXP i.MX platform, and features a CV64A 64-bit core running at up to 1.5GHz and built on the RV64GC RISC-V core IP from the PULP Platform; this is then partnered with a lower-power VC32E coprocessor, based on the PULP Platform’s RV32IMFCXpulp IP.

“NXP is thrilled to be a key contributor to the CORE-V Chassis project leveraging our world class i.MX platform,” adds Rob Oshana, chair of the OpenHW Group board and vice president at NXP. “We see the CORE-V Chassis project as a natural evolution towards enabling OpenHW Group open-source RISC-V cores for high-performance embedded processing.”

The SoC design will also include 3D and 2D graphics processing capabilities, MIPI Display and Camera Serial Interfaces (DSI and CSI), hardware security blocks, PCI Express support, a gigabit Ethernet MAC, USB 2.0 interfaces, support for low- and full-power DDR4 memory, and multiple SDIO interfaces, and will support the Linux operating system.

OpenHW Group has announced an open call for industry participation on the project, advising those interested to reach out to O’Connor via email.