Enjoy Digital has marked off two major milestones in its USB3 PIPE effort to support USB 3.0 on the built-in SerDes high-speed transceivers of major FPGA platforms – using open-source code and an open-source toolchain.
“Current solutions for USB 3.0 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A – SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces) or external FIFO chip (FTDI FT60X or Cypress FX3),” the company explains. “With this project [USB3 PIPE], we want to see if it’s possible to just use the transceivers of the FPGA for the USB3 connectivity and have the USB3 PIPE directly implemented in the fabric (and then avoid any external chip!)”
The answer, it transpires, is “yes:” the company has announced that it has succeeded in getting a functional USB 3.0 link working on Lattice Semiconductor ECP5 and Xilinx 7-series FPGA platforms – all using the built-in SerDes functionality, no external chips required.
“Our FPGA expert has been hard at work and just got her first USB 3.0 link established with Xilinx 7-Series transceivers and full open-source code,” the company announced earlier this month via its official Twitter account – the expert jokily credited with the work being a thoroughly-entertained-seeming small child enjoying a bash away at the development system. “Our expert just also got a first USB 3.0 link up with ECP5 SERDES,” the company continued mere days later, “using full open-source code and toolchain!”
More information on the USB3 PIPE project, which is planned to expand to cover additional protocols including PCI Express and DisplayPort in the future, can be found on the Enjoy Digital GitHub repository.
Cobham Gaisler and fentISS have confirmed that the now-funded De-RISC project is forging ahead with its efforts to built a RISC-V based space-qualified computing platform centred in Europe, in partnership with Barcelona Supercomputing Centre and Thales.
“With the first RISC-V based, fully European platform for space, De-RISC will guarantee access to made-in-Europe technology for aerospace applications,” claims Paco Gomez Molinero, chief executive officer of fentISS and coordinator of the De-RISC project, “thus contributing to the Technologies for European Non-dependence and Competitiveness programme in these strategic markets.”
The Dependable Real-time Infrastructure for Safety-critical Computer (De-RISC) project, which was officially unveiled in early October, has a €3.4 million budget for the development of a European-native space and aviation computing platform. The four companies involved have planned out a system which uses a multi-core system-on-chip designed around the free and open RISC-V instruction set architecture (ISA) by Cobham Gaisler and running the fentISS XtratuM hypervisor. Barcelona Supercomputing Centre, meanwhile, is providing multi-core interference mitigation techniques, and Thales will provide real-world testing for aerospace applications.
The project’s objective claims five key features which make De-RISC tempting over current commercial alternatives: A lack of US export restrictions; the unique multi-core interference mitigation from BSC; portability and customisability; high fault tolerance; and future-proofing compared, its maintainers claim, with older SPARC and PowerPC architectures common to space equipment today.
More information on the project is available on the EU Cordis website.
Think Silicon has announced the development of a general-purpose graphics processor (GPGPU) with 3D acceleration capabilities built on the free and open RISC-V instruction set architecture (ISA) – and claims it is the first in the industry to demonstrate such a device working.
“Building a GPGPU on RISC-V instruction set architecture is another significant milestone in the young history of Think Silicon,” says Think Silicon’s senior vice president for sales and marketing Ulli Mueller of the company’s decision to adopt the ISA. “With the announcement of NEOX|V, we’re delivering the essential low-power GPU technologies to enable companies to create efficient and nimble solutions for a wide variety of markets.”
“The elegance and simplicity of the RISC-V ISA used in NEOX|V will enable a new class of SoCs,” adds chief technology officer Iakovos Stamoulis, “which are smaller, consume less energy and are easier and more open to program.”
The company is hoping that developers will look towards RISC-V for both central (CPU) and graphics (GPU) processing in low-power embedded systems, talking of a new approach to programming which would allow a system to switch a workload between CPU and GPU seamlessly – in contrast to current GPUs, which use a very different architecture to CPUs and can only run specially-constructed code.
Think Silicon has not yet announced commercial availability of the NEOX|V family.
Microchip has opened an early access programme for its RISC-V-enabled PolarFire SoC family of field-programmable gate arrays (FPGAs), providing what the company claims is “the world’s first hardened real-time Linux-capable RISC-V-based microprocessor subsystem” to a low-power FPGA range.
“Delivering the industry’s first RISC-V based SoC FPGA along with our Mi-V ecosystem, Microchip and its Mi-V partners are driving innovation in the embedded space, giving designers the ability to develop a whole new class of power-efficient applications,” claims Bruce Weyer, vice president of the Field Programmable Gate Array business unit at Microchip. “This in turn will allow our clients to add unprecedented capabilities at the edge of the network for communications, defence, medical, and industrial automation.”
The company claims that the PolarFire SoC family draws around 50 percent less power than equivalent competing devices, and will be the first to market with a “deterministic, coherent RISC-V CPU cluster and a deterministic L2 memory subsystem enabling Linux plus real-time applications.”
The early access programme is available to “qualified customers” now on application, Microchip has confirmed, using the Libero SoC 12.3 FPGA design suite and SoftConsole 6.2 integrated development environment for design and the popular Renode framework for debug. The company has also confirmed support in its Mi-V ecosystem from companies including WindRiver, Mentor Graphics, WolfSSL, ExpressLogic, Veridify, Hex Five, and FreeRTOS.
Anyone interested in participating in the programme is asked to apply via email.
OpenHW Group has announced a project to create a heterogeneous multi-core processor evaluation system-on-chip (SoC) design, featuring a high-performance 64-bit core coupled with a lower-power 32-bit core: the CORE-V Chassis.
“The CORE-V Chassis project will help validate that serious silicon development is possible utilising the ethos of open-source hardware, IP, and tools,” claims OpenHW Group president and chief executive Rick O’Connor. “With the tape out of a functional evaluation SoC during the second half of 2020, we will demonstrate that the open hardware mindset is as capable and dependable as any of today’s closed-source alternatives.”
The design in question is based on the NXP i.MX platform, and features a CV64A 64-bit core running at up to 1.5GHz and built on the RV64GC RISC-V core IP from the PULP Platform; this is then partnered with a lower-power VC32E coprocessor, based on the PULP Platform’s RV32IMFCXpulp IP.
“NXP is thrilled to be a key contributor to the CORE-V Chassis project leveraging our world class i.MX platform,” adds Rob Oshana, chair of the OpenHW Group board and vice president at NXP. “We see the CORE-V Chassis project as a natural evolution towards enabling OpenHW Group open-source RISC-V cores for high-performance embedded processing.”
The SoC design will also include 3D and 2D graphics processing capabilities, MIPI Display and Camera Serial Interfaces (DSI and CSI), hardware security blocks, PCI Express support, a gigabit Ethernet MAC, USB 2.0 interfaces, support for low- and full-power DDR4 memory, and multiple SDIO interfaces, and will support the Linux operating system.
OpenHW Group has announced an open call for industry participation on the project, advising those interested to reach out to O’Connor via email.
Free and open source silicon pioneer Cobham Gaisler has announced two new processor IP families, the SPARC-based LEON5 and the RISC-V-based NOEL-V, which enter the company’s family of space-qualified products.
“Cobham has a long-standing tradition of delivering open source solutions in order to expedite the development of next-generation computing devices for the space industry. For nearly 20 years, Cobham’s LEON processors, which are based on the SPARC ISA, have been used in RadHard and High Reliability microelectronics solutions in hundreds of spacecraft and terrestrial applications due to their rich feature set and dependability,” says Kevin Jackson, vice president and general manager, space and semiconductor solutions, Cobham. “Our new LEON5 achieves a major improvement in terms of compute performance, while simultaneously allowing a smooth upgrade path and software re-use for our existing LEON user base.”
The LEON5, though, is only half the story. Cobham has also announced NOEL-V, which marks its first Cobham Gaisler product to be built around at 64-bit implementation of the free and open RISC-V instruction set architecture rather than the company’s usual choice of 32-bit SPARC ISA. “Cobham is delighted to add our first in-house implementation of a RISC-V processor core to our existing processor portfolio,” says Sandi Habinc, general manager for Cobham Gaisler solutions. “The addition of a product line of RISC-V processors strengthens Cobham’s abilities to offer reliable processor solutions to customers also outside the space domain.”
Cobham has confirmed that both processor families will be integrated into the company’s open-source GRLIB VHDL IP core library, and that a partnership with Xilinx will see the new IP certified on the company’s space-ready FPGAs at launch on Christmas Day.
More information on NOEL-V and LEON5 are available on their respective product pages.
Finally, RISC-V specialist SiFive has announced the SiFive Learn Inventor, a development board aimed at the education and maker markets which merges the popular BBC micro:bit design with its own HiFive1.
Launched via crowdfunding in late 2016, though not shipping in volume until January 2017, the SiFive HiFive1 took its design inspiration from the Arduino Uno microcontroller development board but with a Freedom E310 RISC-V chip at its heart. The SiFive Learn Inventor takes a more recent revision of that same chip and mixes things up with a new board design which owes more than a nod to the BBC micro:bit.
The board, designed for the education and maker markets, combines the Freedom E310 32-bit RISC-V chip, running at 150MHz and including 64kB of static RAM and 512kB of flash storage, with an Espressif ESP32 microcontroller for Bluetooth and Wi-Fi communications. A BBC micro:bit style edge connector provides large GPIO connectors for crocodile clips and smaller ones for expansion boards, while the front of the board features a 6×8 RGB LED matrix display and two user-configurable push buttons.
As with the BBC micro:bit, the board includes a three-axis accelerometer, magnetometer, and thermometer, along with an ambient light sensor. Power is provided via micro-USB, also used to program the board, or using a battery connector supporting voltages as low as 2.3V.
The board has been developed in partnership with Amazon’s Web Services division, and includes compatibility with the FreeRTOS real-time operating system as well as the AWS IoT Core cloud compute service. The first units are scheduled to ship in mid-December, with UK reseller Pimoroni taking pre-orders for £40.80.