Tag: RISCV

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

BBC Picks SiFive’s RISC-V-Powered HiFive Inventor for Doctor Who Coding Push

The BBC has announced a partnership with SiFive to bring RISC-V-powered development to kids around the world with the launch of the BBC Doctor Who HiFive Inventor educational development board and supporting coursework bundle. Announced late last year, the SiFive Learn Inventor is a hand-shaped educational development board inspired… Read More

SiFive VIU75 Accelerates Vector Math

At the Linley Fall Conference 2020, SiFive Chief Architect and co-founder Krste Asanovic announced the RISC-V based VIU7 series. In that, the VIU75 CPU core is 64-bit, runs Linux, and supports “RV vector extension”. Read More

SiFive Announces FU740-Based RISC-V PC, Plans to Grow the RISC-V Ecosystem

RISC-V pioneer SiFive has announced its intention to encourage growth of the RISC-V developer ecosystem with the release of a ready-to-run off-the-shelf RISC-V-powered personal computer built on its FU740 processor – offering a turnkey alternative to the current raft of do-it-yourself options. The free and open-source RISC-V instruction set architecture… Read More

ONiO Unveils Energy-Harvesting, Ultra-Low-Power ONiO.zero RISC-V Microcontroller

Internet of Things start-up ONiO has announced a new RISC-V microcontroller, the ONiO.zero, which it claims can be powered purely using energy harvested from the radio-frequency spectrum – no batteries required. “ONiO.zero is an ultra-low-power wireless MCU that uses energy harvesting technology,” ONiO, which focuses on the healthcare side of… Read More

CRU: RISC-V Aplenty, USB3 PIPE Success, An Educational Dev Board, and More

Enjoy Digital has marked off two major milestones in its USB3 PIPE effort to support USB 3.0 on the built-in SerDes high-speed transceivers of major FPGA platforms – using open-source code and an open-source toolchain. “Current solutions for USB 3.0 connectivity with an FPGA require the use of an external… Read More

Cobham Gaisler Announces SPARC-Based LEON5, RISC-V NOEL-V Processor IP

Free and open source silicon pioneer Cobham Gaisler has announced two new processor IP families, the SPARC-based LEON5 and the RISC-V-based NOEL-V, which enter the company’s family of space-qualified products. “Cobham has a long-standing tradition of delivering open source solutions in order to expedite the development of next-generation computing devices… Read More

Microchip Open Early Access Programme for RISC-V-Enabled PolarFire SoC FPGA Family

Microchip has opened an early access programme for its RISC-V-enabled PolarFire SoC family of field-programmable gate arrays (FPGAs), providing what the company claims is “the world’s first hardened real-time Linux-capable RISC-V-based microprocessor subsystem” to a low-power FPGA range. “Delivering the industry’s first RISC-V based SoC FPGA along with our Mi-V… Read More

OpenHW Group Unveils CORE-V Chassis SoC Project, Building on PULP Project IP

OpenHW Group has announced a project to create a heterogeneous multi-core processor evaluation system-on-chip (SoC) design, featuring a high-performance 64-bit core coupled with a lower-power 32-bit core: the CORE-V Chassis. “The CORE-V Chassis project will help validate that serious silicon development is possible utilising the ethos of open-source hardware, IP,… Read More

Dependable Real-time Infrastructure for Safety-critical Computer (De-RISC) Aims for the Stars

Cobham Gaisler and fentISS have confirmed that the now-funded De-RISC project is forging ahead with its efforts to built a RISC-V based space-qualified computing platform centred in Europe, in partnership with Barcelona Supercomputing Centre and Thales. “With the first RISC-V based, fully European platform for space, De-RISC will guarantee access… Read More

SiFive Unveils Learn Inventor Educational RISC-V Development Board

RISC-V pioneer SiFive has announced the SiFive Learn Inventor, a development board aimed at the education and maker markets which merges the popular BBC micro:bit design with its own HiFive1. Launched via crowdfunding in late 2016, though not shipping in volume until January 2017, the SiFive HiFive1 took its… Read More

Think Silicon to Demonstrate its NEOX|V RISC-V GPGPU at the RISC-V Summit 2019

Think Silicon has announced the development of a general-purpose graphics processor (GPGPU) with 3D acceleration capabilities built on the free and open RISC-V instruction set architecture (ISA) – and claims it will be the first in the industry to demonstrate such a device working, at the RISC-V Summit later this… Read More

Bootlin’s Michael Opdenacker Gets You Started with Embedded Linux on RISC-V in Just 40 Minutes

Bootlin’s Michael Opdenacker has published a guide to getting started with embedded Linux on RISC-V in just 40 minutes, as part of a presentation given during the Capitole du Libre 2019 event earlier this month. Building on a presentation first given at the Libre Software Meeting 2005, in which… Read More