Tag: RISC-V

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

Alibaba Unveils High-Performance 16-Core 2.5GHz RISC-V Chip Design

Alibaba, via the Pingtouge (T-Head) division of its DAMO Academy, has announced what it claims is the world’s most powerful processor based on the open RISC-V instruction set architecture (ISA): a 16-core 2.5GHz design built on a 12nm process node, dubbed the CoreXuanTie910 or XT910. “The breakthrough is more than… Read More

Microchip Shows Off Rad-Hardened RISC-V for Low-Cost Satellites

Microchip’s Dorian Johnson has penned a piece on the open RISC-V instruction set architecture (ISA)’s ascent into space, courtesy of radiation-hardened implementations from his company. “Using the new open RISC-V architecture, the FPGA circuitry can operate advantageously close to a remote measurement source,” Johnson explains in the piece for Elektroniikkalehti. Read More

Microsemi CreativeBoard FPGA development board

RISC-V Foundation Launches Security-Focused Soft-Core CPU Contest

The RISC-V Foundation, in partnership with Microchip Technology and Thales, has announced its second soft-core CPU competition – time time focusing on security. Following on from its first soft-core CPU contest late last year, the RISC-V Foundation has announced its second. Where the first focused on performance and smart… Read More

Western Digital Partners with SiFive, PlatformIO for Extended Open-Source Dev Toolset

Western Digital has announced a partnership with SiFive and PlatformIO Labs which will see the latter’s embedded development platform extended in order to provide a vendor-agnostic, end-to-end open environment with full RISC-V support. Western Digital’s interest in embedded development in general and the open RISC-V instruction set architecture (ISA) specifically… Read More

Work Continues on Debian Linux RISC-V Port, Documentation Efforts

The Debian Linux distribution’s Manuel Montezelo has written of the progress in porting the distribution to the 64-bit RISC-V architecture, boasting of around a 90 percent package compatibility milestone. Announced back in April 2018, the Debian Linux RISC-V port had a long road ahead of it. At launch, around… Read More

X-FAB, Efabless Announces RISC-V-Based Raven Mixed-Signal SoC

X-FAB Silicon Foundries and Efabless Corporation have announced the creation of a new mixed-signal system-on-chip (SoC) reference design boasting a RISC-V core: Raven. Designed, its creators claim, in just three months, the open-source mixed-signal Raven SoC was built using an open-source tool set put together by Efabless. Its PicoRV32 32-bit… Read More

European Processor Initiative Delivers First Architectural Designs

The European Processor Initiative (EPI) has announced the delivery of its first architectural designs to the European Commission, marking the first steps in its efforts to create a made-in-Europe processor family for high-performance and automotive computing. Launched in December 2018, the European Processor Initiative boasts 26 industry partners – up… Read More

CRU: ‘Unhackable’ Chips, Grove AI HAT, RISC-V Drones, and More

Researchers from the University of Michigan have announced a new RISC-V processor design with a strong focus on security, using ‘churn’ to keep attackers from exploiting vulnerabilities. “Today’s approach of eliminating security bugs one by one is a losing game,” claims Todd Austin, professor of computer science and engineering at… Read More

Western Digital’s Zvonimir Bandić Offers an Intro to SweRV Core

Western Digital’s Zvonimir Bandić has published an introduction to the company’s open SweRV Core, which it has released to the public following its efforts to move to the RISC-V instruction set architecture (ISA) for its future storage processing products. Western Digital unveiled the SweRV Core late last year, making… Read More

PULP Platform Partners with GreenWaves, Bitcraze for RISC-V AI Drone Controller

The Parallel Ultra-Low Power (PULP) Platform has announced a partnership between ETH Zurich, Greenwaves Technology, and Bitcraze to develop a PULP-powered and wireless artificial intelligence module for drone use: the AI Deck. Based on the earlier PULP-Shield, built as part of the PULP-DroNet project, the AI Shield is designed to… Read More

OpenPiton+Ariane Workshops Scheduled for WOSH, ISCA in June

The OpenPiton project has announced a pair of workshops centred around its OpenPiton+Ariane platform, taking place in Zurich during the Week of Open Source Hardware (WOSH) and Arizona as part of International Symposium on Computer Architecture (ISCA). Created in partnership with the Parallel Ultra-Low Power (PULP) Platform, OpenPiton+Ariane combines… Read More

Seeed Studio Opens Pre-Orders for RISC-V-based Grove AI HAT Board

Seeed Studio has begun taking pre-orders for its Grove AI HAT for Edge Computing, an artificial intelligence-focused accelerator add-on for the Raspberry Pi which is based on the RISC-V Kendryte K210 processor. Based on the Sipeed MAIX M1 module, a development board for which the company crowdfunded late last… Read More