X-FAB Silicon Foundries and Efabless Corporation have announced the creation of a new mixed-signal system-on-chip (SoC) reference design boasting a RISC-V core: Raven.

Designed, its creators claim, in just three months, the open-source mixed-signal Raven SoC was built using an open-source tool set put together by Efabless. Its PicoRV32 32-bit RISC-V processing core runs at 100MHz in bench testing, with simulations suggesting its clock rate could be boosted to 150MHz. Wedded to Efabless’ open-source top-level design is proprietary analogue IP from X-FAB – which, the company points out, was also developed using an open-source design flow.

“The successful partnership with Efabless demonstrates X-FAB’s continued commitment to open-source semiconductor development,” claims X-FAB’s Ulrich Bretthauer. “Nearly 75 percent of Raven’s die area is covered by X-FAB standard library blocks and macros. Using these proven IP blocks increased the reliability of the Raven while minimising first-silicon risk.”

“This project would not have been possible without the support of X-FAB,” adds Mohamed Kassem, Efabless co-founder and chief technical officer, of the partnership. “They have been an early adopter of the Efabless open-innovation model and this project is the logical extension of our collaboration.”

The first Raven chips have been produced on X-FAB’s XH018 180nm six-metal process, which the company states meets automotive quality requirements. For those interested in its design, the Raven SoC is available on the Efabless Design Catalogue with no licence fee attached.