The OpenPiton project has announced a pair of workshops centred around its OpenPiton+Ariane platform, taking place in Zurich during the Week of Open Source Hardware (WOSH) and Arizona as part of International Symposium on Computer Architecture (ISCA).
Created in partnership with the Parallel Ultra-Low Power (PULP) Platform, OpenPiton+Ariane combines the former’s 64-bit application-class RISC-V processor design with the OpenSPARC-based OpenPiton research processor – designed, its creators claim, to form “the go-to multicore environment for Ariane.”
Those eager to learn about the combined platform will have two chances to do so this June, OpenPiton’s Jonathan Balkind has announced, during a pair of hands-on workshops.
“The first tutorial is part of the Week of Open Source Hardware (WOSH) in conjunction with the RISC-V Workshop Zurich,” Balkind explains. “It is a half-day tutorial on Thursday afternoon, June 13th, at ETH Zurich, Switzerland. The second tutorial is in conjunction with ISCA/FCRC 2019 in Phoenix, Arizona. It is a half-day tutorial on Sunday afternoon, June 23rd.
“Both tutorials are hands-on sessions which will first introduce attendees to our validation infrastructure using open-source simulators. Attendees will also learn how to synthesise multiple Ariane RISC-V cores to FPGA and get direct experience with booting multicore RISC-V Linux on our provided FPGAs. We will also teach attendees how to configure and extend the OpenPiton architecture to enable research in architecture, systems, security, EDA, and beyond.”
More information on the workshops, plus links to register, can be found on the OpenPiton blog.