Western Digital’s Zvonimir Bandić has published an introduction to the company’s open SweRV Core, which it has released to the public following its efforts to move to the RISC-V instruction set architecture (ISA) for its future storage processing products.
Western Digital unveiled the SweRV Core late last year, making the source code available in late January under a permissive licence. Based on the RISC-V ISA, the SweRV Core has seen what Western Digital chief technical officer Martin Fink describes as a “gratifying response” from the community, though an analysis by Tom Verbeure reached the conclusion that its design is better suited to professional rather than hobbyist use.
For those eager to learn more, WD’s Zvonimir Bandić has penned an introduction to the project for All About Circuits. “SweRV Cores fill an important void in the spectrum of open-source RISC-V cores,” Zvonimir writes by way of introduction. “How is SweRV Core different? It issues up to two instructions per clock cycle, and a nine-stage pipeline with four execution units, a load/store unit, a two-cycle multiplier, and out-of-pipe 34-cycle divider units. Most open-sourced RISC-V designs – at least designs that we are familiar with from RISC-V conferences and events – are implemented as single-issue pipelines with a number of stages between two and six.”
Zvonimir’s full piece, which goes into how the SweRV Core’s pipeline is accelerated to offer performance close to an Intel Xeon server processor as measured in CoreMarks-per-megahertz, can be found on All About Circuits now.