Researchers from the University of Michigan have announced a new RISC-V processor design with a strong focus on security, using ‘churn’ to keep attackers from exploiting vulnerabilities.

“Today’s approach of eliminating security bugs one by one is a losing game,” claims Todd Austin, professor of computer science and engineering at the University of Michigan and one of the developers behind the design, dubbed Morpheus. “People are constantly writing code, and as long as there is new code, there will be new bugs and security vulnerabilities. With Morpheus, even if a hacker finds a bug, the information needed to exploit it vanishes 50 milliseconds later. It’s perhaps the closest thing to a future-proof secure system.”

The processor works, its creators claim, by ‘churning’ instructions and data – encrypting and shuffling them about – 20 times a second. A watchdog checks for likely attacks, and if a threat is detected ups the churn rate – which, at the default 50 millisecond level, is claimed to have a mere one percent impact on the processor’s performance.

While the true security of the Morpheus design will only be proven once it is in the hands of third-party researchers, its creation highlights how RISC-V and other free and open source silicon (FOSSi) efforts are seeing rapid adoption in research projects as a means of quickly creating a prototype of a new design – something not so easily achieved with proprietary equivalents like x86 and Arm.

A paper on the Morpheus design, which is to be commercialised by Agita Labs, has been published in the ACM Digital Library as part of the Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems.

The Gentoo Linux distribution has announced initial, experimental support for the free and open RISC-V instruction set architecture (ISA).

“After some preparations, we’re happy to announce (initially experimental) support for a new arch: riscv,” writes Andreas Huettel in the gentoo-dev mailing list. “The keyword is ‘~riscv’; no stable keyword will be used in the beginning.”

Details on the support, which has been confirmed as working using the QEMU emulator on non-RISC-V hardware, can be found on the project wiki. The overall goal is, the organisation explains, to bring first-class support for the RISC-V architecture to Gentoo, though initially the support will be entirely experimental with testing on RISC-V hardware scheduled for some time in the future.

Gentoo is only the latest in a string of platforms adding RISC-V support since the Linux kernel received an official port: Amazon’s FreeRTOS kernel, Fedora Linux, and a range of Buildroot-compatible platforms are all now available for RISC-V. Gentoo’s approach differs to most, however: packages are provided as source and compiled on the host device, rather than compiled on a remote build system and distributed in binary form, allowing for improved client-specific optimisations that can help boost performance on resource-constrained systems.

More information is available on the Gentoo wiki.

Seeed Studio has begun taking pre-orders for its Grove AI HAT for Edge Computing, an artificial intelligence-focused accelerator add-on for the Raspberry Pi which is based on the RISC-V Kendryte K210 processor.

Based on the Sipeed MAIX M1 module, a development board for which the company crowdfunded late last year, the Grove AI HAT features a dual-core 64-bit RISC-V CPU running at 600MHz along with a 16-bit neural network co-processor dubbed the Kendryte Processing Unit (KPU), a dedicated hardware floating-point unit (FPU), and an audio processor with support for up to eight external microphones, plus connectivity for an LCD panel and camera. Board features are then exposed using Seeed’s Grove connector design, with the board operating as either a standalone single-board computer or connecting to a Raspberry Pi as a co-processor using the Hardware Attached on Top (HAT) form factor.

“We have released varies of Sipeed AI products, we believe it is time to make it Grove and bring all our hundreds of grove senors and grove actuators to your AI applications,” the company explains. “So here comes the Grove AI HAT for Edge Computing. We’ve added six Grove connectors to this hat, including 1x Digital IO, 2x Analog IO, 1x I2C, 1x UART, and 1x PWM. On top of that, based on [the] kendryte-standalone-sdk, we added the full Arduino Core API interface to support Arduino IDE, Linux, Windows, Mac OS X, and other development environments. Which means you can run Grove Arduino Libraries and many excellent Arduino libraries on this board easily.”

The board is scheduled to launch in mid-June, priced at $28.90 per unit; this is reduced to $24.50 during the pre-order period. More details are available on the official product page.

The Parallel Ultra-Low Power (PULP) Platform has announced a partnership between ETH Zurich, Greenwaves Technology, and Bitcraze to develop a PULP-powered and wireless artificial intelligence module for drone use: the AI Deck.

Based on the earlier PULP-Shield, built as part of the PULP-DroNet project, the AI Shield is designed to control a Crazyflie 2.0 micro-drone. The original design partnered GreenWaves’ GAP8 RISC-V system-on-chip with two off-chip memories, a QVGA ultra-low-power camera, and the control pins required to have the device fly the drone under control of the DroNet convolutional neural network (CNN.)

“[AI Deck] is a collaborative product between GreenWaves Technologies, ETH Zurich and Bitcraze,” says Bitcraze’s Tobias Antonsson of the upgraded design. “It is based on the PULP-Shield that the Integrated and System Laboratory has designed. The difference with the PULP-Shield is that we have added a ESP32, the NINA-W102 module, so that video can be streamed over WiFi. This we hope will ease development and add more use cases.”

The AI Deck is due to be demonstrated by Bitcraze during the International Conference on Robotics and Automation (ICRA) in Montreal next week, with more information available on the Bitcraze blog. Additional details on the PULP-DroNet project and PULP-Shield can be found in another blog post on the site.

Western Digital’s Zvonimir Bandić has published an introduction to the company’s open SweRV Core, which it has released to the public following its efforts to move to the RISC-V instruction set architecture (ISA) for its future storage processing products.

Western Digital unveiled the SweRV Core late last year, making the source code available in late January under a permissive licence. Based on the RISC-V ISA, the SweRV Core has seen what Western Digital chief technical officer Martin Fink describes as a “gratifying response” from the community, though an analysis by Tom Verbeure reached the conclusion that its design is better suited to professional rather than hobbyist use.

For those eager to learn more, WD’s Zvonimir Bandić has penned an introduction to the project for All About Circuits. “SweRV Cores fill an important void in the spectrum of open-source RISC-V cores,” Zvonimir writes by way of introduction. “How is SweRV Core different? It issues up to two instructions per clock cycle, and a nine-stage pipeline with four execution units, a load/store unit, a two-cycle multiplier, and out-of-pipe 34-cycle divider units. Most open-sourced RISC-V designs – at least designs that we are familiar with from RISC-V conferences and events – are implemented as single-issue pipelines with a number of stages between two and six.”

Zvonimir’s full piece, which goes into how the SweRV Core’s pipeline is accelerated to offer performance close to an Intel Xeon server processor as measured in CoreMarks-per-megahertz, can be found on All About Circuits now.

The CHIPS Alliance, a Linux Foundation-backed consortium for free and open source silicon (FOSSi) efforts, has announced in inaugural workshop for the 19th of June at Google’s Sunnyvale, California facility.

Launched back in March, the CHIPS Alliance includes among its founding members Google, Western Digital, Esperanto, and SiFive, all but one of which has announced or shipped products based on the open RISC-V instruction set architecture (ISA). Its first workshop will, its organisers claim, provide project details, strategies, and roadmaps from member companies, while attendees will be given the opportunity to propose register transfer level (RTL) projects and ideas for improving development flow.

“This workshop at Google will kick off CHIPS Alliance hardware RTL development,” explains Western Digital’s Dr. Zvonimir Bandic, chair of the CHIPS Alliance Foundation. “The organisation will discuss the planned projects, what is needed for accelerated open source hardware and key software tools. Attendees will see the potential of CHIPS Alliance and the vision for what we will deliver.”

“Workshop attendees will learn more about our organisation and the open source hardware, verification flows/tools and software we will be developing. Attendees will also have an opportunity to suggest projects and meet with CHIPS Alliance members and the Board of Directors,” adds Google’s Dr. Richard Ho, board member of the Foundation. “We look forward to answering questions, discussing ideas and sharing the aspirations of the group.”

The confirmed agenda sees talks on the Federation open-source chip design workflow, a collaborative end-to-end design verification flow, an update on the BooM v2 project and the Blue Cheetah framework, alongside a look at open-source tools including cocotb, Chisel, FIRRTL, and FuseSoC.

More information about the event is available on the CHIPS Alliance website.

Finally, the OpenPiton project has announced a pair of workshops centred around its OpenPiton+Ariane platform, taking place in Zurich during the Week of Open Source Hardware (WOSH) and Arizona as part of International Symposium on Computer Architecture (ISCA).

Created in partnership with the Parallel Ultra-Low Power (PULP) Platform, OpenPiton+Ariane combines the former’s 64-bit application-class RISC-V processor design with the OpenSPARC-based OpenPiton research processor – designed, its creators claim, to form “the go-to multicore environment for Ariane.”

Those eager to learn about the combined platform will have two chances to do so this June, OpenPiton’s Jonathan Balkind has announced, during a pair of hands-on workshops.

“The first tutorial is part of the Week of Open Source Hardware (WOSH) in conjunction with the RISC-V Workshop Zurich,” Balkind explains. “It is a half-day tutorial on Thursday afternoon, June 13th, at ETH Zurich, Switzerland. The second tutorial is in conjunction with ISCA/FCRC 2019 in Phoenix, Arizona. It is a half-day tutorial on Sunday afternoon, June 23rd.

“Both tutorials are hands-on sessions which will first introduce attendees to our validation infrastructure using open-source simulators. Attendees will also learn how to synthesise multiple Ariane RISC-V cores to FPGA and get direct experience with booting multicore RISC-V Linux on our provided FPGAs. We will also teach attendees how to configure and extend the OpenPiton architecture to enable research in architecture, systems, security, EDA, and beyond.”

More information on the workshops, plus links to register, can be found on the OpenPiton blog.