Tag: FOSSi

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

Fedora Releases RISC-V Disk Images, Praises QEMU Patch Set

Support for Linux on the open RISC-V instruction set architecture (ISA) continues to improve, with patches to the QEMU emulator proving stable enough for the Fedora project to build and distribute RISC-V bootable disk images. Announced on the RISC-V software development mailing list late last night by Red Hat’s… Read More

PULP Releases 64-bit Linux-Compatible Ariane RISC-V Core IP

The Parallel Ultra Low Power (PULP) Platform project has announced the release of Ariane, a Linux-compatible 64-bit application-class RISC-V core design, published under the permissive Solderpad Hardware Licence. A joint effort between ETH Zurich and the University of Bologna, Ariane marks the pair’s first high-performance application-class RISC-V core intellectual property… Read More

PULPissimo RISC-V Microcontroller Core Released

The PULP (Parallel Ultra Low Power) Platform, a joint project between ETH Zurich and University of Bologna, has announced the release of the PULPissimo RISC-V microcontroller core, designed to take over from the more basic PULPino – and is also teasing a 64-bit multi-core Linux-ready RISC-V core dubbed Ariane. “Today… Read More

CRU: Events, HiFive Unleashed, Open ASIC Design and More

The Free and Open Source Silicon Foundation has announced that ORConf 2018 will be held over the weekend of September 21st to 23rd in Gdansk, Poland. Now in its seventh year, ORConf is a free-to-attend conference for open source digital, semiconductor, and embedded systems design engineers. What started… Read More

Bunnie Huang on Open-Source, Low-Cost ASIC Design

The Institute of Electrical and Electronics Engineers (IEEE) has published an interview with noted engineer Andrew ‘Bunnie’ Huang on the topic of how small teams can design custom silicon in a constrained budget. “FPGAs [Field Programmable Gate Arrays] waste a large amount of silicon compared with an ASIC [Application… Read More

Multi-core 64-bit Linux-capable RISC-V Board Unveiled and Available to Pre-order

HiFive Unleashed demonstrated at FOSDEM 2018 running Linux, presentation software and a Quake port, with first boards to ship in around 8 weeks time. In a presentation entitled, Igniting the Open Hardware Ecosystem with RISC-V, we first heard from SiFive’s Palmer Dabbelt, who provided a background to… Read More

Busting the RISC-V ISA Myths

Electronic Design is continuing its 11 Myths series, which covered LoRaWAN last month, with a look at the RISC-V open instruction set architecture (ISA). “Many companies today are exploring free, open-source hardware and software as an alternative to closed, costly instruction set architectures (ISAs). RISC-V is a free, open,… Read More

ORConf 2018 Announced

The Free and Open Source Silicon Foundation has announced that ORConf 2018 will be held over the weekend of September 21st to 23rd in Gdansk, Poland. Now in its seventh year, ORConf is a free to attend conference for open source digital, semiconductor and embedded systems design engineers. Read More

CRU: OSHCamp 2018, OpenPiton, LoRaWAN and More

The Open Source Hardware Camp 2018 is set to take place in Lincoln on the 30th of June and 1st of July, and the call for talks and workshops is now open. While the event has an overall theme of, naturally, open source hardware, there is no overriding topic list… Read More

OSDDI: Jonathan Balkind, OpenPiton

Back in 2006 Sun Microsystems made the bold move of open sourcing the RTL code for their UltraSPARC T1 processor via the OpenSPARC project. Targeted at data centre applications and with a full configuration featuring 8x cores and 32x hardware threads, the processor was used in Sun and Fujitsu systems,… Read More

FOSSi Foundation Opens Call for Google Summer of Code Projects

The Free and Open Source Silicon (FOSSi) Foundation has announced a call for proposals as part of its application to the Google Summer of Code event, which has previously borne fruit including the recreation of a classic computer on modern hardware. An educational initiative run by advertising giant Google each… Read More

LowRISC 0.5 Brings First Ethernet Support

The lowRISC project has officially announced the launch of lowRISC 0.5, a milestone release of the popular RISC-V implementation which brings with it open-source Ethernet support. Built upon a RISC-V implementation from the University of California at Berkeley (UC Berkeley), lowRISC 0.5 marks a major milestone release on the… Read More