The Institute of Electrical and Electronics Engineers (IEEE) has published an interview with noted engineer Andrew ‘Bunnie’ Huang on the topic of how small teams can design custom silicon in a constrained budget.
“FPGAs [Field Programmable Gate Arrays] waste a large amount of silicon compared with an ASIC [Application Specific Integrated Circuit], so the cost floor, which depends in large part of the surface area of silicon required for the chip, is often an order of magnitude higher than you’d want it to be,” Bunnie explains of the reasons a small start-up may want to build custom silicon. “But fabricating an ASIC isn’t cheap either.
“There are some open-source tools that might be able to get you there. The ‘SCMOS‘ design rules are the most workable. As for design software, you can use an open-source toolchain based on Magic (Xcircuit, IRSIM, NetGen, Qrouter, and Qflow). All to say, down to around maybe the 180-nanometer technology node (or so), you could get away with using open-source tools. Smaller than that, though, requires doing really funny stuff with the mask imaging and using shapes that aren’t just simple polygons anymore. And the design kits from various vendors to accomplish that get more and more closed. 180nm is pretty ‘big’ by today’s standards. But if you really wanted to place some special combination of circuits on a single silicon die, you could do it this way. And it could lead to some novel products that would otherwise be impossible with discrete designs.”
The full interview is available on the IEEE Spectrum site now.