Tag: RISC-V

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

PULP Platform Announces RISC-V HERO Heterogeneous Research Platform

The Parallel Ultra-Low Power (PULP) Platform team has announced the release of its latest creation: HERO, the open heterogeneous research platform combining an FPGA-based RISC-V many-core accelerator with an Arm Cortex-A host processor. “HERO combines a PULP-based open-source parallel many-core accelerator implemented on FPGA with a hard ARM Cortex-A multicore… Read More

Western Digital's Martin Fink and Steffen Hellmold

Western Digital CTO: RISC-V Offers “A Clean Sheet of Paper”

Western Digital has released a short video discussing how the open RISC-V instruction set architecture is changing its vision for data processing, as it pledges to ship billions of RISC-V cores in its future products. Western Digital had previously pledged support for the open RISC-V instruction set architecture with the… Read More

Darkriscv RISC-V Implementation LST file

Darkriscv: An Overnight BSD-Licensed RISC-V Implementation

Developer Marcelo Samsoniuk has demonstrated just how flexible the open RISC-V instruction set architecture is by creating his own implementation – in, he claims, just one night. “Developed in a magic night of 19 Aug, 2018 between 2am and 8am, the darkriscv is a very experimental implementation of the open… Read More

SiFive, Nvidia Partner for RISC-V, NVDLA Edge AI SoC

RISC-V pioneer SiFive has announced a partnership with graphics and Arm-based processor giant Nvidia to integrate the former’s RISC-V core intellectual property with the latter’s deep-learning acceleration IP in a single high-performance system-on-chip (SoC) design. “Nvidia open sourced its NVDLA [Nvidia Deep Learning Architecture] architecture to drive the adoption of… Read More

Zephyr Project RTOS Gets RISC-V Partners, Board Support

The Zephyr Project, which maintains an eponymous open-source real-time operating system (RTOS) for the Internet of Things (IoT) under The Linux Foundation, has announced partnerships with SiFive and Antmicro to add RISC-V support to the platform. “RISC-V is about creating open source platforms for the entire world to collaborate on,… Read More

Bluespec Releases Apache-Licensed Piccolo RISC-V Core

Massachusetts-based Bluespec, a founding member of the RISC-V Foundation, has released the first entry in its open-source RISC-V processor family: the 32-bit three-stage Piccolo. Designed, the company explains, for Internet of Things (IoT) and other embedded uses, the small-footprint Piccolo design uses the 32-bit RV32IM variant of the open RISC-V… Read More

SiFive HiFive1 Board, Courtesy of SiFive

CRU: RISC-V SSDs, Open Satellite Radio, LoRaWAN 1.0.3, and More

This fortnight has been a strong one for the open RISC-V instruction set architecture, starting with the news that IIT Madras has partnered with Intel and HCL Technologies to create an I/O-packed microcontroller test chip in 22nm FinFET that takes aim at ARM Cortex A35/A55 and has successfully booted Linux… Read More

Mobiveil Partners with SiFive for RISC-V-based Programmable Storage

SiFive’s implementation of the open RISC-V instruction set architecture (ISA) has scored another design win, this time to power a smart reprogrammable storage device aimed at the data centre and enterprise markets from Mobiveil. Fresh from the announcement of the world’s first RISC-V based SSD controller and SSD implementation… Read More

Fadu Announces World’s First RISC-V SSD, Controller

Fadu, a fabless semiconductor company specialising in the memory and storage markets, has announced the launch of the world’s first RISC-V based solid state drive (SSD) controller, the Annapurna, based on SiFive’s E51 multi-core IP. Beating Western Digital, which announced its own plans to switch from proprietary instruction set architectures… Read More

RISC-V Architecture SHAKTI Test Chip Boots Linux

IIT Madras partner with Intel Corporation and HCL Technologies to create I/O packed microcontroller test chip in 22nm FinFET that takes aim at ARM Cortex A35/A55. In a presentation at the RISC-V workshop hosted at the Indian Institute of Technology (IIT) Madras in July, researchers shared details of a… Read More

Silicon Dreams: RISC-V from Emulation to FPGA to ASIC

When working with brand-new silicon designs, particularly free and open source silicon, there’s a bit of a bootstrapping issue: you want to write software for the new silicon, but there’s no silicon yet available; nobody wants to go to the expense of making the silicon, meanwhile, when there’s no software… Read More

RISC-V Foundation’s SSC Calls on Big Data, Defence Companies

RISC-V Foundation director Ted Speers has offered up more details on the organisations he would like to see involved in the recently-announced Security Standing Committee. Announced earlier this month by executive director Rick O’Connor, the RISC-V Foundation’s Security Standing Committee came with a request: “[A] call to action for… Read More