This fortnight has been a strong one for the open RISC-V instruction set architecture, starting with the news that IIT Madras has partnered with Intel and HCL Technologies to create an I/O-packed microcontroller test chip in 22nm FinFET that takes aim at ARM Cortex A35/A55 and has successfully booted Linux on the design.
In a presentation at the RISC-V workshop hosted at the Indian Institute of Technology (IIT) Madras in July, researchers shared details of a collaboration between the SHAKTI project, Intel and HCL, which resulted in a chip that has successfully booted Linux and supports the secure L4 microkernel.
The test chip was fabricated in 22nm FinFET, with a 4x4mm die and flip-chip packaging, achieving an operating frequency of 320MHz at a core voltage of 0.7v. The SHAKTI C-class device boasts no less than 324 signal I/Os and targets mid-range embedded systems operating around 200-400MHz, with ARM Cortex A35/A55 squarely in its sights.
The researchers also cover the verification tooling used and explain how they wrote an in-house automatic assembly generator to create test programs, which are sent to a Spike RISC-V simulation serving as a golden reference, plus the SHAKTI C-class SoC, with an equivalence check that looks for a deviation from the expected output.
For further details see the presentation video and slides. Those looking for a more general introduction to the SHAKTI project may be interested in our interview with project members for the OSDDI series, which was filmed at ORConf back in 2015.
Fadu, a fabless semiconductor company specialising in the memory and storage markets, has announced the launch of the world’s first RISC-V based solid state drive (SSD) controller, the Annapurna, based on SiFive’s E51 multi-core IP.
Beating Western Digital, which announced its own plans to switch from proprietary instruction set architectures to the open RISC-V ISA late last year, to the punch, Fadu’s Annapurna is claimed to have market-leading specifications: at one third the power and one third the footprint of competing proprietary cores, the SiFive E51 RISC-V implementation in the Annapurna controller pushes 3.5GB/s and 800,000 input/output operations per second (IOPS) performance in the flagship Bravo enterprise-grade SSD at a 6-8W active power draw.
“Fadu is focused on building the most advanced memory and storage devices for our customers and addressing their ongoing needs,” explains Jihyo Lee, Fadu’s chief executive. “SiFive’s RISC-V Core IP was 1/3 the power and 1/3 the area of competing solutions, and gave Fadu the flexibility we needed in optimising our architecture to achieve these groundbreaking products.”
“The flexibility, 64-bit, embedded and multicore features of the E51 RISC-V Core IP is ideal for the storage market and we’re excited to be closely partnered with Fadu, who was able to quickly take advantage of RISC-V and deliver a true world-leading product,” adds Jack Kang, vice president of product at SiFive. “SiFive looks forward to working with FADU as they continue to build next-generation products for the SSD industry.”
More information on the Annapurna controller and Bravo SSD are available from the Fadu website.
SiFive’s implementation of the open RISC-V instruction set architecture (ISA) can also be found at the heart of another storage product, this time powering a smart reprogrammable storage device aimed at the data centre and enterprise markets from Mobiveil.
RISC-V pioneer SiFive has confirmed a design win that will see the company’s E51 and U54 multi-core RISC-V intellectual property (IP) used in Mobiveil’s reprogrammable FPGA-based solid-state storage products.
“We chose to partner with SiFive on this SSD platform solution as their cores offer the lowest area and highest power efficiency of any similar cores in the market,” claims Ravi Thummarukudy, Mobiveil’s chief executive, of the partnership. “Mobiveil’s advanced FPGA-based board enables reliable and robust system solutions that can be easily tailored by enterprise and data centre designers. Having a RISC-V CPU in an FPGA, designers can optimise their solution to target [the] latest flash devices from multiple suppliers. Furthermore, the FPGA-based board solution enables enterprise and data center designers the flexibility to re-architect how storage is deployed in their high-performance cloud.”
“RISC-V is the ideal processor for data centre storage applications,” adds Shafy Eltoukhy, senior vice president of operations at SiFive Inc. “The cores’ highly efficient microarchitecture and configurability provide the optimal performance needed to execute the latest storage programs data centres are employing to accelerate access to the exploding amounts of information being compiled today. Working together with Mobiveil to make this RISC-V based SSD platform enables customers to accelerate their RISC-V based product development efforts.”
Satellite imaging specialist Planet Labs has announced the launch of OpenLST, an open hardware satellite radio platform for communication with remote vehicles, instruments, and stations using low-cost commercial-off-the-shelf (COTS) components.
“Radio system design is often viewed as a ‘black box’ that is out of reach to all but the most experienced of engineers. This leads many educational groups to commercial radio solutions, which are often very expensive, difficult to integrate, and can unintentionally drive other elements of design,” explains Planet’s Bryan Klofas of the project’s inspiration. “A poorly understood radio subsystem can be fatal to any project. For example, communications subsystems contribute to at least 29 percent of CubeSat failures in the first 90 days on-orbit.
“OpenLST is designed with an existing and proven radio using inexpensive and widely available commercial, off-the-shelf parts. Planet releases it today with the goal of lowering the barriers to entry for engineers and engineering projects of all kinds. The OpenLST transceiver is approximately six by five centimeters with a mass of 20 grams. This radio operates on the UHF band and provides 3.5 kilobit per second user data rates. The design also provides time-of-flight ranging that can be used to estimate link distance.”
The design files for OpenLST, which measures 6x5cm and weighs 20g, are available under the Creative Commons Attribution Share-Alike 4.0 (CC-BY-SA 4.0) licence, which allows for reuse with or without modification including for commercial purposes so long as the original creator is credited and the resulting files released under the same licence.
All files are available through Planet’s self-hosted Git repositories, detailed at the end of the announcement post.
A group of developers, lawyers, and security researchers have joined forces to launch disclose.io, an effort to produce a standardised framework for security disclosures which provide protections for good-faith researchers and the companies whose products they analyse.
The field of security research can be a lucrative one: many companies offers ‘bug bounty’ programmes which invite security experts to analyse software and hardware for vulnerabilities and privately report them so they can be fixed ahead of public disclosure, with payouts ranging from a free T-shirt to hundreds of thousands of dollars. Where no formal programme exists, and in some cases even if a programme exists but the research is declared to be out-of-scope, there can also be the danger of being sued for their actions.
Disclose.io aims to fix that, building on Bugcrowd and CipherLaw’s Open Source Vulnerability Disclosure Framework (OSVDF), Amit Elazari’s Legal Bug Bounty programme, and a call from cloud storage giant Dropbox to better protect good-faith security researchers.
The project’s core terms, available on its GitHub repository, list a set of guidelines companies can adopt in order to both protect researchers and, following that protection, encourage them to communicate vulnerabilities without the fear of reprisal. Those adopting the framework receive the right to use the logo as a form of guarantee which, it is hoped, will attract security research talent.
More information on the project is available on the official website, while technology news site Ars Technica has a more detailed write-up.
The LoRa Alliance has announced an update to the LoRaWAN 1.0.3 specification for low-power wide-area wireless networks, adding unicast and multicast support to Class B devices and new time synchronisation features for other classes.
In its latest update to the open LoRaWAN low-power wide-area network standard, proving popular globally for Internet of Things and other distributed sensor applications, the LoRa Alliance has added two major new features: unicast and multicast support for devices in the Class B category, the first of the two optional added-feature device categories which build upon the mandatory Class A category.
As well as the new Class B functionality, the Class A and Class C categories have received an extra bit of polish in the form of a new time synchronisation feature using the “DeviceTimeRequest” MAC command. These, however, are less dramatic: the Alliance suggests that anyone implementing a Class B device should upgrade to the latest version of the LoRaWAN specification as soon as possible, those implementing Class A or Class C devices can continue using the earlier release.
The three LoRaWAN device categories are defined as bi-directional end devices (Class A), bi-directional end devices with scheduled receive slots (Class B), and bi-directional end devices with maximal receive slots (Class C), each allowing for decreased latency at the cost of increased power requirements.
The new LoRaWAN 1.0.3 specification is available now from the official website (PDF warning).
Chinese technology giant Tencent, meanwhile, has announced its membership of the LoRa Alliance, as part of a plan to launch a LoRaWAN-based Internet of Things (IoT) network in the bustling city of Shenzhen.
“It is clear that LPWANs [low-power wide area networks] are essential for IoT technology and applications, and the market is quickly growing in China,” explains Hongtao Bei, Tencent Technologies’ vice president, of the company’s decision to join the LoRa Alliance, “especially in areas like government public services, industry manufacturing, personal IoT devices, etc.”
“LoRaWAN has seen rapid growth, and we feel it is highly complementary to NB-IoT [narrowband Internet of Things] in the LPWAN market,” adds Huixing Wang, vice president of Tencent Cloud. “Joining the LoRa Alliance will allow us to influence LoRaWAN development, advance IoT adoption, and strengthen our cloud business by building close partnerships with other LoRaWAN vendors around the world.”
The membership is far from a box-ticking exercise, too: Tencent, which is one of the largest technology companies in China, has announced it will use the LoRa Alliance’s open LoRaWAN standard to launch a wide-area network in the technology hub city of Shenzhen, along with the launch of a range of IoT-focused products and services designed to assist with its use.
More information is available from the official press release.
Finally, we at AB Open have discussed the process of developing and working with real-world RISC-V implementations, starting at the emulation level and working up to a fully-realised physical application specific integrated circuit (ASIC).
In a piece dubbed ‘Silicon Dreams,’ we look at the key bootstrapping issue facing RISC-V and other novel instruction set architectures: you want to write software for the new silicon, but there’s no silicon yet available; nobody wants to go to the expense of making the silicon, meanwhile, when there’s no software to use it.
The answer is a three-pronged approach: emulation, soft-core implementations running on a field-programmable gate array (FPGA), and finally application-specific integrated circuits (ASICs) – the latter of which are, for the first time, becoming accessible as far down as the hobbyist level thanks to initiatives like OnChip’s Itsy-Chipsy.
The full piece can be read on the AB Open website.