Tag: FOSSi

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

MIT Unveils World’s First RISC-V Carbon Nanotube Processor, RV16XNano

Researchers from the Massachusetts Institute of Technology (MIT), working with Analog Devices, have announced the production and execution of the world’s first 16-bit programmable processor built around carbon nanotube field-effect transistors (CNFETs) – and they’ve implemented the open RISC-V instruction set architecture (ISA) on it. One of a range of… Read More

DARPA Takes RISC-V SSITH Voting Machine Prototype to DEF CON 2019

The US Defence Advanced Research Projects Agency (DARPA) has unveiled the first prototype of its System Security Integrated Through Hardware and Firmware (SSITH) platform for future electronic voting machines, based on an in-house RISC-V processor. Announced back in 2017, the SSITH programme sees researchers working on securing future computing systems… Read More

CRU: LoRaWAN World Records, SweRVolf SoC, OpenPower, and More

The Things Network, the community-driven LoRaWAN project, has announced a world record successful transmission distance from the Servet project: 476 miles, or 766 kilometres. Designed for low power yet wide area use, LoRaWAN is the technology behind community-driven wide-area networking project The Things Network – the largest open LoRaWAN network… Read More

GigaDevice Unveils Low-Cost GD32V RISC-V Microcontroller

GigaDevice, a company which has previously concentrated on microcontrollers built around the proprietary Arm instruction set architecture (ISA), has released a new part based on the open RISC-V ISA: GD32V. First spotted by RISC-V pioneer Sipeed late yesterday, the GigaDevice GD32V is based on the Nucleisys N20x RISC-V core,… Read More

IBM, OpenPOWER Foundation Make POWER ISA Open At Last

IBM’s OpenPOWER Foundation, set up to build the POWER architecture ecosystem, has made a milestone announcement: it is to make the POWER instruction set architecture, along with key hardware designs and supporting technologies, available under an open source licence. Announced along with the news that the OpenPOWER Foundation is to… Read More

QEMU 4.1.0 Extends RISC-V Open ISA Support

The open-source QEMU machine emulator and virtualiser has received enhanced support for the open RISC-V instruction set architecture (ISA) in its 4.1.0 release. Following on from the 4.0.0 release back in April, QEMU 4.1.0 brings a range of improvements to its support for the open RISC-V ISA. Chief among… Read More

Researchers Publish Roadmap for RISC-V Opportunities in Space Tech

Researchers at the Delft University of Technology have published a roadmap which seeks to maximise the potential of the open RISC-V instruction set architecture (ISA) for space applications across the full range of requirements from low-power microcontrollers up to high-end payload processors for artificial intelligence applications. “This paper proposes a… Read More

CHIPS Alliance Launches FuseSoC-Based SweRVolf System on Chip Design

CHIPS Alliance has launched a system-on-chip (SoC), built using Western Digital’s open-source SweRV Core and the FuseSoC build toolset, dubbed SweRVolf A collaboration between FuseSoC creator and maintainer Olof Kindgren, Western Digital Director of Next Gen Platforms Tech Zvonimir Bandic, outgoing chief technology officer Martin Fink, and CHIPS Alliance, SweRVolf… Read More

Andes Technology Points to Explosive RISC-V Growth

Andes Technology has announced explosive demand for its proprietary processor cores based on the open RISC-V instruction set architecture (ISA), highlighting the growing demand for alternatives to x86, Arm, MIPS, and other proprietary ISAs. Born from the University of California at Berkeley in 2010, the open RISC-V instruction set architecture… Read More

Alibaba Unveils High-Performance 16-Core 2.5GHz RISC-V Chip Design

Alibaba, via the Pingtouge (T-Head) division of its DAMO Academy, has announced what it claims is the world’s most powerful processor based on the open RISC-V instruction set architecture (ISA): a 16-core 2.5GHz design built on a 12nm process node, dubbed the CoreXuanTie910 or XT910. “The breakthrough is more than… Read More

CRU: RISC-V Soft-Core Contest, Wuthering Bytes Programme, Plan 9 for Raspberry Pi, and More

The RISC-V Foundation, in partnership with Microchip Technology and Thales, has announced its second soft-core CPU competition – time time focusing on security. Following on from its first soft-core CPU contest late last year, the RISC-V Foundation has announced its second. Where the first focused on performance and smart… Read More

PULP Platform Tapes Out Urania Heterogeneous RISC-V ASIC

The Parallel Ultra-Low Power (PULP) Platform project has announced tape-out of Urania, an implementation of its bigPULP design which combines one Ariane core with two quad-core RISC-V clusters. Announced back in February last year, Ariane is a 64-bit application-class RISC-V core design, created as a joint effort between ETH… Read More