CHIPS Alliance has launched a system-on-chip (SoC), built using Western Digital’s open-source SweRV Core and the FuseSoC build toolset, dubbed SweRVolf
A collaboration between FuseSoC creator and maintainer Olof Kindgren, Western Digital Director of Next Gen Platforms Tech Zvonimir Bandic, outgoing chief technology officer Martin Fink, and CHIPS Alliance, SweRVolf is a functional system-on-chip (SoC) design built around WD’s open-source SweRV EH1 RISC-V core. The design also builds on contributions from elsewhere in the free and open source silicon community.
“The idea is to offer a portable and extendable SoC for FPGA and simulation to experiment with the SweRV EH1 core,” award-winning engineer Kindgren explains. “Initially targets the Digilent Nexys A7 FPGA board and simulations with Modelsim or Verilator. Using FuseSoC this can quickly be ported to other targets too.
“This is also a testament to the vibrant FOSSi ecosystem as it combines IP cores and tools from many different developers and groups around the world to create a fully open source project that can be used in industry, academia or by curious hobbyists. To give some examples, apart from Western Digital’s CPU most AXI infrastructure comes from PULP Platform, DDR2 controller from Enjoy Digital, OpenOCD integration by M Labs, and others. Debug IF leans on lowRISC work, my very own FuseSoC and many more.”
The SoC launch, files and details for which are available on the CHIPS Alliance GitHub repository, comes as long-time RISC-V supporter and Western Digital chief technology officer Martin Fink announces his retirement. He is to be replaced by Dr. Siva Sivaram in the newly-formed role of President of Technology and Strategy, but will remain with the company in an advisory capacity for “matters relating to data centre architectures, including RISC-V.”