The RISC-V Foundation, in partnership with Microchip Technology and Thales, has announced its second soft-core CPU competition – time time focusing on security.
Following on from its first soft-core CPU contest late last year, the RISC-V Foundation has announced its second. Where the first focused on performance and smart use of available resources, though, the second has a very different focus: security.
“With the proliferation of connected devices, security is one of the key challenges in hardware design. The free and open RISC-V ISA presents an incredible opportunity for the ecosystem to collaborate to develop more robust solutions for the growing security demands of today and the future,” explains Calista Redmond, chief executive of the RISC-V Foundation. “This contest is an opportunity for designers and hardware enthusiasts to rethink what is possible with computing design and build a secure RISC-V soft CPU that can prevent software security attacks.”
The contest, which targets Microchip’s Creative Development Board and its IGLOO 2 field-programmable gate array (FPGA), has three price levels: first place receives €5,000, a HiFive Unleashed development board, and an expansion board for same; second place receives €2,000 and a HiFive Unleashed board; and third place €1,000 and a HiFive Unleashed board. Entries will be judged on each design’s ability to resist five common attacks, total resource usage, expected power consumption, and points deducted for each change made to the compiler.
Interested parties can enter the competition on the RISC-V Foundation website. All entries must be written in Verilog, or a framework which generates Verilog as its output, and capable of running the Zephyr real-time operating system (RTOS) version 1.14. Entries need to be in by the 15th of September, and must be based on the RV32IMC ISA and have their sources publicly released.
The Shakti Processor Project, which has produced India’s first natively-manufactured processor, has publicly released the Shakti Software Development Kit (SDK) – meaning application development for the RISC-V based chips can now begin.
Featured in one of AB Open’s Open Source Digital Design Insights (OSDDI) interviews, the Shakti Processor Project from IIT Madras has been going from strength to strength: after targeting early 2018 for initial manufacturing of the RISC-V-based parts, the team booted Linux on a 22nm part produced in a foreign manufacturing facility then on India’s first natively-manufactured processor using a 180nm process node from the Indian Space Research Organisation (ISIRO) Semiconductor Laboratory in Chandigarh.
With hardware in hand and an operating system booted, the team has turned its attention to a software ecosystem with the public release of the Shakti Software Development Kit (SDK). Released under the GNU General Public Licence 3, the Shakti SDK “provides a platform to develop standalone applications and projects” for what its creators aim to be a family of processors ranging from the low-power embedded E- and controller C-class parts up to the multi-core mainstream S-class and high-performance computing (HPC) H-class parts.
The SDK is available now on the Shakti GitLab repository.
The Parallel Ultra-Low Power (PULP) Platform project has announced tape-out of Urania, an implementation of its bigPULP design which combines one Ariane core with two quad-core RISC-V clusters.
Announced back in February last year, Ariane is a 64-bit application-class RISC-V core design, created as a joint effort between ETH Zurich and the University of Bologna. RI5CY, meanwhile, is a 32-bit RISC-V core design popularised by the PULPissimo microcontroller platform. Now, the pair have been combined in a single system-on-chip (SoC) dubbed Urania, for the Urania Sternwarte observatory in Zurich – itself named for the Greek muse of astronomy.
“We have recently taped out a couple of chips. One of them is Urania, [a] BigPULP implementation with one Ariane core and two clusters each with 4x RI5CY cores and a DDR interface,” the PULP Platform team announced via Twitter this week. “Urania is a big leap forward,” adds PULP’s Luca Benini. “We never tried so many new things in a single SoC. Exciting ride: thanks to Andreas, Beat and the team for the heroic effort!”
Designed on a 64nm process node, targeting a 100MHz clock and packaged as QFN64, the Urania SoC marks the first application-specific integrated circuit (ASIC) implementation of the bigPULP architecture, first unveiled as part of the HERO Heterogeneous Research Platform. In its initial design, the chip includes a single 64-bit Ariane core and two clusters of four 32-bit RI5CY cores with floating-point units (FPUs), alongside the PULPo first-order optimisation hardware acceleration unit and a DDR3 memory interface.
More details on Urania can be found on the project website.
Kunal Gulati, working with the OpenPiton Project’s Jonathan Balkind and Katie Lim under the Free and Open Source Silicon Foundation (FOSSi) Google Summer of Code, has announced a project to expand the JuxtaPiton heterogeneous research processor with a third core: ao486.
Announced back in November 2018, JuxtaPiton is the merging of the SPARC v9-based OpenPiton with Clifford Wolf’s PicoRV32 RISC-V core in a single open-source research processor design. “When implemented on FPGA, JuxtaPiton can boot Debian Linux on an OpenSPARC core as with OpenPiton,” OpenPiton’s Jonathan Balkind explained at the time. “With the addition of a PicoRV32 core in the system, the OpenSPARC core can offload the execution of RISC-V binaries to be natively executed on the PicoRV32 core. When the RISC-V binary needs to make a system call, it can proxy it on the OpenSPARC core instead.”
Now, JuxaPiton is getting a third open core: an i486-compatible core dubbed ao486. “In this iteration of JuxtaPiton, we are trying to augment the infrastructure with the open-source ao486 core which is i486 compatible providing x86 ISA support connected with the OpenSPARC T1’s SPARC v9,” explains Kunal Galati, who is working on the project under the FOSSi Foundation as part of the Google Summer of Code programme. “This kind of system allows us to re-use a lot of x86 legacy code (our first priority is obviously Doom) and is capable of booting Windows 95 or Linux Kernel(till version 3.13).”
The project is still in the early stages, with much of the work focused on the software side to ensure the core will be able to boot correctly. Full details are available in Gulati’s Medium post.
Microchip’s Dorian Johnson has penned a piece on the open RISC-V instruction set architecture (ISA)’s ascent into space, courtesy of radiation-hardened implementations from his company.
“Using the new open RISC-V architecture, the FPGA circuitry can operate advantageously close to a remote measurement source,” Johnson explains in the piece for Elektroniikkalehti. “It enables autonomous data collection, condition monitoring, and load control at the payload source, thus freeing up resources from the satellite CPU system since it does not have to be responsible for controlling the remote payload unit.
“As a standard open architecture maintained by the RISC Foundation, RISC-V ISA offers many benefits in the design of space technology. One benefit is the ‘frozen’ instruction set, which means that any software written to the RISC-V kernel will always work on any RISC-V device. This allows the original code base to be reused in many different software for decades, making it much easier to maintain older applications. Partners and resellers can create RISC-V software kernels that are tailored to customer specific requirements and enable RTL sharing when needed to monitor security-critical applications.
“RISC-V processors have already been tested in radiation-resistant FPGAs for aerospace applications,” Johnson concludes. “An FPGA comprising a RISC-V processor is suitable for use in each payload unit to read, measure and make decisions based on remote measurement data transmitted by the LX7730 mixed signal circuit, and to report information on the condition of the payload unit to or special non-standardized protocols.”
Microchip’s proof-of-concept is the Six Sensor Demo, a radiation-hardened RTG4 FPGA running a RISC-V soft-core linked to an LX7730 remote sensing controller over an SPI bus. It’s not alone in aiming to take an open ISA into space, however: the TechEdSat-1 cubesat was deployed to the International Space Station in October 2012 with an OpenRISC processor at its heart, while Cobham Gaisler produces OpenSPARC-based radiation-hardened Leon processors.
Johnson’s full piece, translated from Finnish, is available on Elektroniikkalehti.
The programme for the Wuthering Bytes Festival Day, which headlines a 10 day long celebration of technology in picturesque Hebden Bridge, has now been finalised ahead of its opening on Friday the 30th of August 2019.
Since its inception in 2013, Wuthering Bytes has attracted a top-quality collection of technologists, futurists, and enthusiasts from a range of disciplines – everyone from musicians and printing-press operators to rocket scientists and radio hams. Each gives a talk on their particular field of expertise, sometimes including active demonstrations – and they are always well-received by an appreciative audience, as well as setting the tone for the remainder of the Wuthering Bytes activities over the course of the week.
The event’s organisers, AB Open’s Andrew Back has now confirmed the final programme for the 2019 Festival Day. Keynoting the event will be JP Rangaswami, information scientist, with a talk entitled The Future of Lurk; composer and maker Sarah Angliss will give a talk on fellow composer, sci-fi author, and self-taught physicist Muriel Howorth; David Fletcher, meanwhile, will use his talk, Powering the Valley Over Time, to look at the first 500 years of the Upper Calder Valley.
The most electrifying presentation, meanwhile, is likely to come from Extreme Electronics’ Derek Woodroffe, who will be offering an Introduction to Tesla Coils – including live demonstrations of his lightning-throwing creations. Finally, Red Tin Tunes’ Dave Ives and Gnac and The Montgolfier Brothers’ Mark Tranmer will be DJing the after party, while scavenger-poets Rag and Bone will be demonstrating The Lost and Found Tree in the Town Hall Courtyard.
An effort to port the Plan 9 from Bell Labs operating system to the Raspberry Pi family of low-cost single-board computers has received initial support for the new Raspberry Pi 4 – though there’s still work to do on the project.
First released in 1992 for academic users and 1995 for the general public, Plan 9 from Bell Labs – named for infamous Ed Wood sci-fi effort Plan 9 from Outer Space – replaced Unix as the telecommunications company’s primary research platform. Despite being defocused by the company in 1996 and having never reached the popularity of Linux or BSD, Plan 9 from Bell Labs lives on: 2000 saw a free third edition released and 2002 the fourth edition, which continues to be updated – including new support for the Raspberry Pi 4 single-board computer.
“I’m not suggesting anyone should rush out to buy a [Raspberry Pi 4] just yet,” writes Richard Miller in a post to the 9fans mailing list. “Unlike previous releases of the board, this incarnation has some very big changes, so a lot of new driver writing will be needed before it’s at all useful under Plan 9. It’s quite daunting actually.
“[It] boots as far as the root prompt, but there are too many new peripherals without driver support (or documentation so far) to do anything useful: USB host sockets are all connected to new USB 3 controller; SD card is connected to new eMMC controller (can’t use sdhost); Ethernet is connected to new native GBE controller. Wifi is unchanged from 3B+, but currently fails intermittently with emmc IO_RW_EXTENDED data corruption.”
Those already running Plan 9 from Bell Labs can get access to Miller’s kernel source with the command “srv -nq tcp!9p.io sources /n/sources”; anyone else can find it via web browser.
The Free and Open Source Silicon (FOSSi) Foundation has announced the three-month countdown to ORConf, the conference for anyone interested in open-source silicon and the tool chains behind it.
“ORConf is in its 8th year of bringing the open source silicon community together for a weekend of presentations, ideas and discussions,” writes FOSSi Foundation director Julius Baxter of the event, which this year is being held in Bordeaux, France on the 27th to 29th of September. “We hope many of our fine past attendees will make the trip to France to join us again for what should be another fantastic event.
“Presentation submissions are now open. We welcome everyone to come and tell us about your project, endeavour or your open source silicon use story. The call for sponsors goes out again this year – ORConf isn’t free to run and we rely on the generous support of companies and individuals to help put the event on. At this stage all sponsorship opportunities are available – so if you’d like to help the FOSSi Foundation fund the event, and get a great bit of recognition for it, then please get in touch with us.”
Those interested in attending can register on the ORConf website; those attending in a professional capacity are asked to purchase a ticket; anyone interested in presenting can submit a proposal now; and all additional information is available on the official website.
Engineer Pepijn de Vos has released the source code and video demonstration for a five-chip 74-series logic gate ‘breathing LED circuit’ – without ever having had to manually design the printed circuit board.
“I had been keeping an eye on Yosys, the open source HDL synthesis tool, which can apparently do ASIC by giving it a liberty file that specifies the logic cells your foundry supports,” de Vos explains. “Meanwhile I also toyed with the idea of making a 7400 series computer, and I wondered if you could write a liberty file for 7400 chips. I had kind of dismissed the idea, but then ZirconiumX [Dan Ravensloft] came along and did it.
“It suffices to say this revived my interest in the idea and a lively discussion and many pull requests followed. First some small changes, then simulations to verify the synthesised result is still correct, and finally a KiCad netlist generator. You see, generating a Yosys netlist is nice, but eventually these 7400 chips have to end up on a PCB somehow. Normally you draw your schematic in Eeschema, generate a netlist, and import that to Pcbnew. But instead I used skidl to generate the netlist directly. Then all there is to do is add the inputs and outputs and run the autorouter (or do it manually of course).
“This was all done in Verilog, so where is the VHDL, you might wonder. Well, Yosys does not really support VHDL yet, but Tristan Gingold is hard at work making GHDL synthesise VHDL as a Yosys plugin. I think this is very important work, so I’ve been contributing there as well. After some pull requests I was able to port the breathing LED to VHDL.”
De Vos’ full write-up, and linkes to the source code, can be found on his blog, while the resulting circuit is demonstrated in the embedded video.
Finally, the OpenROAD project, the University of California at San Diego’s initiative to reduce the cost, expertise, and risk barriers to hardware design through open-source, has opened nominations for Open-Source Community Contribution Awards.
“The OpenROAD project is pleased to announce the establishment of its Open-Source Community Contribution Awards,” the organisation explains of its launch, which brings with it the promise of financial recompense for open-source and open-hardware developers. “New open-source contributions in the realm of physical implementation and validation for IC, package or board design can be nominated for an Award. Awards in the range of US $250 to US $2000 will be made periodically by an industry review panel led by Dr. Paul Penzes (VP Engineering, Qualcomm).”
There are a few rules to note, however: anyone who has received project funding from OpenROAD within the last 12 months is not eligible for OSCCA; taxes may be taken from the award amount; and priority will be given to projects which are made available under permissive licences including BSD, MIT, and Apache, and to those that interoperate well with existing workflows – both open and proprietary. Self-nominations are, however, welcomed.
Those interested in applying can find an application form on the official website, along with an email address for any questions.