News

The latest on developments at AB Open and across the wider community.

CERN-OHL v 2.0 Licensed Design by Sam Smith

CERN Launches Open Hardware Licence 2.0 in Reciprocal and Permissive Variants

CERN has officially released version 2.0 of its eponymous Open Hardware Licence (CERN-OHL), designed to simplify the language and make it easier to understand as well as broadening its applicability and introducing three variants for specific requirements. “The CERN-OHL is to hardware what the free and open-source licences are to… Read More

RISC-V Foundation Formally Ratifies the Processor Trace Specification

The RISC-V Foundation has announced the formal ratification of the processor trace specification, introducing a standardised trace encoder algorithm for the free and open-source instruction set architecture as a means of assisting with debugging. “RISC-V is rapidly gaining popularity due to its open and modular design that supports customisation on… Read More

The OpenPOWER Foundation Releases Compliance Definitions, Forms ISA Work Group

The OpenPOWER Foundation has officially released the compliance definition for its now-open instruction set architecture, defining test suite requirements for both POWER8 and POWER9 ISAs, and has pledged to form a new Work Group for ISA-related activities. “There is much excitement in the August 2019 announcement of open-sourcing the POWER… Read More

Call for Participation Opens for OSHCamp 2020 Talks, Workshops

The call for participation in the Open Source Hardware Camp (OSHCamp) 2020 has been placed – in the year which marks the Open Source Hardware User Group’s 10th anniversary. Taking place on Saturday the 29th and Sunday the 30th of August in Hebden Bridge Town Hall, West Yorkshire, OSHCamp 2020… Read More

Wuthering Bytes 2020 Call for Participation Now Open

The dates for Wuthering Bytes 2020, the latest in the annual week-long celebration of interesting and inspiring technology, have been confirmed as the 28th of August through to the 6th of September inclusive, and the call for participation is now open. “We’re excited to announce that this year the… Read More

ONiO Unveils Energy-Harvesting, Ultra-Low-Power ONiO.zero RISC-V Microcontroller

Internet of Things start-up ONiO has announced a new RISC-V microcontroller, the ONiO.zero, which it claims can be powered purely using energy harvested from the radio-frequency spectrum – no batteries required. “ONiO.zero is an ultra-low-power wireless MCU that uses energy harvesting technology,” ONiO, which focuses on the healthcare side of… Read More

CRU: RISC-V Aplenty, USB3 PIPE Success, An Educational Dev Board, and More

Enjoy Digital has marked off two major milestones in its USB3 PIPE effort to support USB 3.0 on the built-in SerDes high-speed transceivers of major FPGA platforms – using open-source code and an open-source toolchain. “Current solutions for USB 3.0 connectivity with an FPGA require the use of an external… Read More

Cobham Gaisler Announces SPARC-Based LEON5, RISC-V NOEL-V Processor IP

Free and open source silicon pioneer Cobham Gaisler has announced two new processor IP families, the SPARC-based LEON5 and the RISC-V-based NOEL-V, which enter the company’s family of space-qualified products. “Cobham has a long-standing tradition of delivering open source solutions in order to expedite the development of next-generation computing devices… Read More

Microchip Open Early Access Programme for RISC-V-Enabled PolarFire SoC FPGA Family

Microchip has opened an early access programme for its RISC-V-enabled PolarFire SoC family of field-programmable gate arrays (FPGAs), providing what the company claims is “the world’s first hardened real-time Linux-capable RISC-V-based microprocessor subsystem” to a low-power FPGA range. “Delivering the industry’s first RISC-V based SoC FPGA along with our Mi-V… Read More

OpenHW Group Unveils CORE-V Chassis SoC Project, Building on PULP Project IP

OpenHW Group has announced a project to create a heterogeneous multi-core processor evaluation system-on-chip (SoC) design, featuring a high-performance 64-bit core coupled with a lower-power 32-bit core: the CORE-V Chassis. “The CORE-V Chassis project will help validate that serious silicon development is possible utilising the ethos of open-source hardware, IP,… Read More

Enjoy Digital Announces USB3 PIPE Project Successes for Open-Source USB 3.0 on FPGA SerDes

Dependable Real-time Infrastructure for Safety-critical Computer (De-RISC) Aims for the Stars

Cobham Gaisler and fentISS have confirmed that the now-funded De-RISC project is forging ahead with its efforts to built a RISC-V based space-qualified computing platform centred in Europe, in partnership with Barcelona Supercomputing Centre and Thales. “With the first RISC-V based, fully European platform for space, De-RISC will guarantee access… Read More