Enjoy Digital has marked off two major milestones in its USB3 PIPE effort to support USB 3.0 on the built-in SerDes high-speed transceivers of major FPGA platforms – using open-source code and an open-source toolchain.
“Current solutions for USB 3.0 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A – SuperSpeed 5 Gbps USB 3.0 Transceiver with PIPE and ULPI Interfaces) or external FIFO chip (FTDI FT60X or Cypress FX3),” the company explains. “With this project [USB3 PIPE], we want to see if it’s possible to just use the transceivers of the FPGA for the USB3 connectivity and have the USB3 PIPE directly implemented in the fabric (and then avoid any external chip!)”
The answer, it transpires, is “yes:” the company has announced that it has succeeded in getting a functional USB 3.0 link working on Lattice Semiconductor ECP5 and Xilinx 7-series FPGA platforms – all using the built-in SerDes functionality, no external chips required.
“Our FPGA expert has been hard at work and just got her first USB 3.0 link established with Xilinx 7-Series transceivers and full open-source code,” the company announced earlier this month via its official Twitter account – the expert jokily credited with the work being a thoroughly-entertained-seeming small child enjoying a bash away at the development system. “Our expert just also got a first USB 3.0 link up with ECP5 SERDES,” the company continued mere days later, “using full open-source code and toolchain!”
More information on the USB3 PIPE project, which is planned to expand to cover additional protocols including PCI Express and DisplayPort in the future, can be found on the Enjoy Digital GitHub repository.