Author: Gareth Halfacree

Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.

Embench Embedded Benchmark Project Calls for Aid

A call-to-arms has been raised by the Embench team for assistance in developing a new, fully-open benchmark suite designed to offer embedded developers an alternative to the products of the Embedded Microprocessor Benchmark Consortium (EMBC). As detailed in an article on EE Times, the Embench team is working to… Read More

European Processor Initiative Delivers First Architectural Designs

The European Processor Initiative (EPI) has announced the delivery of its first architectural designs to the European Commission, marking the first steps in its efforts to create a made-in-Europe processor family for high-performance and automotive computing. Launched in December 2018, the European Processor Initiative boasts 26 industry partners – up… Read More

Antmicro Launches Renode 1.7 with TSN, PTP Support, PicoRV32, Murax SoC

Antmicro has announced the release of Renode 1.7 – quickly followed by version 1.7.1 – with the framework’s first support for time-sensitive networking (TSN) and precision time protocol (PTP) on RISC-V platforms. An open-source simulation framework popular among those working within the proprietary Arm and open RISC-V ecosystems, and recently… Read More

CRU: ‘Unhackable’ Chips, Grove AI HAT, RISC-V Drones, and More

Researchers from the University of Michigan have announced a new RISC-V processor design with a strong focus on security, using ‘churn’ to keep attackers from exploiting vulnerabilities. “Today’s approach of eliminating security bugs one by one is a losing game,” claims Todd Austin, professor of computer science and engineering at… Read More

Western Digital’s Zvonimir Bandić Offers an Intro to SweRV Core

Western Digital’s Zvonimir Bandić has published an introduction to the company’s open SweRV Core, which it has released to the public following its efforts to move to the RISC-V instruction set architecture (ISA) for its future storage processing products. Western Digital unveiled the SweRV Core late last year, making… Read More

PULP Platform Partners with GreenWaves, Bitcraze for RISC-V AI Drone Controller

The Parallel Ultra-Low Power (PULP) Platform has announced a partnership between ETH Zurich, Greenwaves Technology, and Bitcraze to develop a PULP-powered and wireless artificial intelligence module for drone use: the AI Deck. Based on the earlier PULP-Shield, built as part of the PULP-DroNet project, the AI Shield is designed to… Read More

OpenPiton+Ariane Workshops Scheduled for WOSH, ISCA in June

The OpenPiton project has announced a pair of workshops centred around its OpenPiton+Ariane platform, taking place in Zurich during the Week of Open Source Hardware (WOSH) and Arizona as part of International Symposium on Computer Architecture (ISCA). Created in partnership with the Parallel Ultra-Low Power (PULP) Platform, OpenPiton+Ariane combines… Read More

Seeed Studio Opens Pre-Orders for RISC-V-based Grove AI HAT Board

Seeed Studio has begun taking pre-orders for its Grove AI HAT for Edge Computing, an artificial intelligence-focused accelerator add-on for the Raspberry Pi which is based on the RISC-V Kendryte K210 processor. Based on the Sipeed MAIX M1 module, a development board for which the company crowdfunded late last… Read More

The CHIPS Alliance Announces Inaugural Workshop Agenda

The CHIPS Alliance, a Linux Foundation-backed consortium for free and open source silicon (FOSSi) efforts, has announced in inaugural workshop for the 19th of June at Google’s Sunnyvale, California facility. Launched back in March, the CHIPS Alliance includes among its founding members Google, Western Digital, Esperanto, and SiFive, all… Read More

Gentoo Linux Announces Experimental RISC-V Support

The Gentoo Linux distribution has announced initial, experimental support for the free and open RISC-V instruction set architecture (ISA). “After some preparations, we’re happy to announce (initially experimental) support for a new arch: riscv,” writes Andreas Huettel in the gentoo-dev mailing list. “The keyword is ‘~riscv’; no stable keyword… Read More

Researchers Turn to RISC-V for High-Security Morpheus Processor Design

CRU: Fieldbus in Linux, FPGA SweRV Core, Wuthering Bytes Tickets, and More

Linux 5.2, the upcoming release of the open source kernel, is to receive an official subsystem for the Fieldbus networking protocol family – bringing built-in support for the monitoring and control of industrial equipment. Spotted by Michael Larabel on the Linux news site Phoronix, the Fieldbus subsystem has been… Read More