Linux 5.2, the upcoming release of the open source kernel, is to receive an official subsystem for the Fieldbus networking protocol family – bringing built-in support for the monitoring and control of industrial equipment.

Spotted by Michael Larabel on the Linux news site Phoronix, the Fieldbus subsystem has been accepted into the Linux 5.2 merge window ahead of the kernel’s stable release in July.

“”The subsystem allows for devices to exchange data over a Fieldbus whether it be Profinet, FLNet, or one of the other implementations. The subsystem provides a generic framework for exposing switches, lights, actuators, motors, and other hardware,” Michael explains. “As part of this initial subsystem is support for the HMS Profinet Card. Profinet is based on Ethernet and uses TCP/IP paired with specialised protocols designed for delivering real-time performance and the ability to integrate with other Fieldbus systems.”

Officially standardised as IEC 61158 and based on precursor technologies including Hewlett-Packard’s HP-IB which became the General Purpose Interface Bus (GPIB) along with Intel’s Multibus and Bitbus, Fieldbus offers a range of claimed improvements over its competitors including lowered cabling requirements and better diagnostic support – though has also come under fire for issues with inter-compatibility between different vendors’ own Fieldbus implementations.

More information on the Linux Fieldbus subsystem can be found in the commit notes.

Western Digital has announced a strong response to the release of its RISC-V based open silicon SweRV Core, along with the availability of an official implementation for field-programmable gate array (FPGA) use.

Announced back in December 2018 as part of a company-wide initiative to transition data processing products away from proprietary cores to alternatives based on the RISC-V instruction set architecture (ISA), released in January this year, and the subject of a deep-dive analysis by Tom Verbeure last month, Western Digital’s SweRV Core is provided under the Apache Licence 2.0 alongside a simulator dubbed Whisper and a cache coherency fabric.

Now, a few months on from the release, Western Digital has claimed a strong community response. “Western Digital is pleased to provide the SweRV Core to the open source community. The initial response and targeted uses are gratifying to the entire development team and all of Western Digital,” claims Martin Fink, Western Digital chief technology officer. “We look forward to the acceleration of the RISC-V ecosystem and the innovations which will result from this core.”

At the same time, Western Digital is listening to community feedback: the original release has now been joined by an FPGA reference design for use with the Digilent Nexus4 DDR platform, giving those looking to get started a leg-up. This, as with WD’s other releases, is made available under the Apache 2.0 licence.

More details on the latest release can be found on the Western Digital blog.

The RISC-V Foundation has released the agenda for its RISC-V Workshop Zurich, to be held on the 11th-13th of June as part of the larger Week of Open Source Hardware (WOSH).

Following its call for speakers, which closed back in February, the RISC-V Foundation has firmed up the schedule for the three-day RISC-V Workshop Zurich 2019 – though only the first two of these days are open to the general public, with the latter being reserved for RISC-V Foundation members.

The agenda includes a keynote speech from Luca Benini, professor at host ETH Zurich, on RISC-V’s potential for energy-efficient computing spanning the spectrum from microwatt embedded systems to exascale supercomputers; official updates from RISC-V Foundation members Krste Asanovic and Ted Marena as well as representatives of the RISC-V Technical Committee; updates on projects including OpenPiton+Ariane, Efabless’ Raven, the PUMP-NN neural network library, the space-qualified Klessydra RISC-V microcontroller, and a talk on how to squeeze eight RISC-V cores into a $38 FPGA development board by Olof Kindgren; a look at the OpenSBI as well as a secure bootloader, protecting RISC-V processors from physical attacks, a look at an intrinsically secure RISC-V processor from Olivier Savry and Thomas Hiscock, and Helena Handschuh on an open source approach to system security; updates on open-source compiler toolchains, RISC-V development via QEMU, and development with FreeRTOS; a look at the debug and trace capabilities in the SweRV core from Western Digital; formal verification of the PULPino core; and a look at RISC-V commercial implementations from SiFive, CloudBEAR, and Syntacore.

The event schedule also includes room for networking and blocks of time for 60-second poster sessions. The third day, meanwhile, is open to RISC-V Foundation members only, and does not yet have a schedule posted publicly.

The full schedule, along with a link to book tickets to attend the event, can be found on the official website. Details on additional events following the RISC-V Workshop Zurich as part of the broader Week of Open Source Hardware, meanwhile, can be found on the FOSSi Foundation website.

Version 4.0.0 of the QEMU emulator has been released, bringing with it new features for those working with the RISC-V instruction set architecture (ISA).

Designed to allow a system to run code designed for a different instruction set, emulation via QEMU or a similar package is a key part of developing for less-common ISAs like RISC-V – allowing a developer to produce software without requiring access to a hardware implementation, whether that’s a soft core on a field-programmable gate array (FPGA) or a hardware application specific integrated circuit (ASIC).

The open-source QEMU emulator has proven popular among those working with RISC-V, and the new 4.0.0 release brings with it some improvements and enhancements on that front. Chief among these are support for Peripheral Component Interconnect (PCI) and Universal Serial Bus (USB) on the ‘virt board’ virtualised development board, support for symmetric multi-processing (SMP) on the SiFive_u virtual machine, and support for transmission interrupts on the SiFive UART.

Other RISC-V improvements include additional fields in mstatus, three states – dirty, clean, and off – for the FS field, support for writing to the misa CSR, and support in the in-built gdbserver for register lists as XML files. These are in addition to a range of improvements and enhancements for other ISAs supported within QEMU.

More information on the new release is available on the QEMU wiki.

Analogue and mixed-signal semiconductor specialist Semtech has announced the full launch of the LoRaWAN Academy, offering free educational modules for everyone from students through to large enterprises looking to develop wireless Internet of Things (IoT) applications.

“Developers are the most important part of any modern technology platform, and the LoRaWAN Academy is there to help them get up to speed on one of the fastest growing IoT-enabling technologies out there today” claims Steven Hegenderfer, senior director of the developer ecosystem in Semtech’s Wireless Sensing and Products Group. “We are working with the LoRaWAN-based ecosystem to develop and drive material that is beneficial to the community. Providing completely free modules focused on building LoRa-based applications gives students, engineers, developers, and enterprises the jump-start they need to build robust, innovative IoT applications.”

Originally launched exclusively for universities in 2017, the revised LoRaWAN Academy is now open to anyone interested in building applications based around LoRa long-range low-power wide area network technologies and the open LoRaWAN protocol. At present, it includes ten modules of self-paced online classes with video lectures, reading materials, and hands-on assignments.

“LoRa Technology is a leading technology and recognised as the de facto platform for developing IoT applications,” adds Dr. S.A. Pasupathy, head of the Department of Electronics and Communication Engineering at Kumaraguru College of Technology (KCT), one of the organisations which has been working with the LoRaWAN Academy. “With the LoRaWAN Academy available for anyone and free, this is a great opportunity for participants to learn and realise the return of investment of LoRa as well as having ability to accelerate their applications to the market and their career growth.”

More information on the Semtech LoRaWAN Academy can be found on the official website.

Dover Microsystems’ Greg Sullivan has written of how Antmicro’s open-source Renode development framework has considerably decreased the length of his company’s design cycle – showcasing why the framework is becoming increasingly popular.

Built with embedded platforms and the Internet of Things (IoT) in mind, Renode allows for the execution, debugging, and testing of embedded software unmodified on a standard off-the-shelf PC, and is proving popular for those designing the hardware itself. Its three-layer design allows the creation of virtual system-on-chip parts from a series of building blocks – including those based on the open RISC-V instruction set architecture – then build the resulting virtual SoC into a virtual hardware device. Each simulation can also support multiple virtual boards over simulated wired or wireless connectivity, further extending the work that can be done before having to move to physical prototypes.

Example case studies published to the official website include Google’s use of Renode to test the TensorFlow Lite machine learning framework, support for the Microsemi PolarFire SoC, the use of Renode as a Zephyr development tool, and even a utilities provider which used Renode to develop hardware based on the EFR32 SoC.

Now, Dover Microsystems’ Greg Sullivan has written of how Renode is an integral part of his company’s hardware-software co-design efforts, and has directly led to a reduction in the design cycle length and the complexity of evaluating said designs.

“The Renode framework’s flexible nature, its open-source availability, and the existence of commercial support provided by its authors made it easy for Dover to first build a prototype implementation of their desired workflow and then contract Antmicro to implement (and release into the open-source domain) functionalities that made Renode even better suited for their use case, such as per-instruction execution,” Greg explains. “In particular, using Renode, Dover engineers are now able to: switch between Arm and RISC-V based integration efforts using the same setup; prototype SoCs (both reference/minimal and customer-defined) at different levels of detail/fidelity.

“The hardware and software teams collaborate on the hardware interface (which of course will continue to evolve). As the hardware team starts implementing blocks in SystemVerilog, the software team creates models of the new blocks in C#, the native language underlying Renode,” Greg continues, outlining the workflow in which Renode sits. “The software team is then able to write firmware that communicates with the new hardware interfaces, and test that software under Renode simulation. Eventually, the software is run on an FPGA emulator.

“It is critical that design teams able to explore a large range of possible hardware/software co-optimisation techniques and tradeoffs, without a large, serialised ‘first-hardware-then-software development process.’ A flexible software functional simulator such as Renode allows Dover engineers to collaborate across the hardware-software divide to find optimal trade-offs between hardware and software complexity, making it integral to their efforts.”

Greg’s full write-up, which was written in partnership with Antmicro’s Michael Gielda, can be found on All About Circuits now. More information on Renode, meanwhile, is available on the official website.

Finally, the first five talks for the Wuthering Bytes Festival Day, to take place in Hebden Bridge on the 30th of August 2019, have now been confirmed – along with an attendee gift kindly supplied by electronics specialist Boldport.

Produced by AB Open as part of its contribution to the community, the first Wuthering Bytes took place in 2013. Organised by Andrew Back and Tim Harbour, the week-long event kicks off with a Festival Day of talks and presentations – five of which have now been confirmed.

“Science writer Georgina Ferry [is] presenting the story of LEO: the world’s first business computer,” Andrew and Tim write on the event announcement. “We will also hear from technology lawyer and CEO of Trustable, Amanda Brock, who will talk about how our perceptions of and interactions with software have profoundly changed — and the need to manage risk and for trustable software.

“We’ll be treated to talks from Ben Cartwright and Jo Hinchliffe, on nanosatellites and how you can build your own satellite ground station! And Michael Dales will explain how anyone can build their own guitar, using some pretty neat non-traditional techniques, via their local community workshop.”

Andrew and Tim have also confirmed that Boldport, specialist in ‘electronic craftsmanship,’ will be providing a gift for all Festival Day attendees: The Tiny Engineer Superhero Emergency Kit soldering project tin.

A small number of early bird tickets are on sale now via Eventbrite, with full sales to open once the full event schedule has been announced. More information is available on the Wuthering Bytes website.