Tag: RISCV

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

QEMU 4.1.0 Extends RISC-V Open ISA Support

The open-source QEMU machine emulator and virtualiser has received enhanced support for the open RISC-V instruction set architecture (ISA) in its 4.1.0 release. Following on from the 4.0.0 release back in April, QEMU 4.1.0 brings a range of improvements to its support for the open RISC-V ISA. Chief among… Read More

Researchers Publish Roadmap for RISC-V Opportunities in Space Tech

Researchers at the Delft University of Technology have published a roadmap which seeks to maximise the potential of the open RISC-V instruction set architecture (ISA) for space applications across the full range of requirements from low-power microcontrollers up to high-end payload processors for artificial intelligence applications. “This paper proposes a… Read More

CHIPS Alliance Launches FuseSoC-Based SweRVolf System on Chip Design

CHIPS Alliance has launched a system-on-chip (SoC), built using Western Digital’s open-source SweRV Core and the FuseSoC build toolset, dubbed SweRVolf A collaboration between FuseSoC creator and maintainer Olof Kindgren, Western Digital Director of Next Gen Platforms Tech Zvonimir Bandic, outgoing chief technology officer Martin Fink, and CHIPS Alliance, SweRVolf… Read More

Andes Technology Points to Explosive RISC-V Growth

Andes Technology has announced explosive demand for its proprietary processor cores based on the open RISC-V instruction set architecture (ISA), highlighting the growing demand for alternatives to x86, Arm, MIPS, and other proprietary ISAs. Born from the University of California at Berkeley in 2010, the open RISC-V instruction set architecture… Read More

CRU: RISC-V Soft-Core Contest, Wuthering Bytes Programme, Plan 9 for Raspberry Pi, and More

The RISC-V Foundation, in partnership with Microchip Technology and Thales, has announced its second soft-core CPU competition – time time focusing on security. Following on from its first soft-core CPU contest late last year, the RISC-V Foundation has announced its second. Where the first focused on performance and smart… Read More

PULP Platform Tapes Out Urania Heterogeneous RISC-V ASIC

The Parallel Ultra-Low Power (PULP) Platform project has announced tape-out of Urania, an implementation of its bigPULP design which combines one Ariane core with two quad-core RISC-V clusters. Announced back in February last year, Ariane is a 64-bit application-class RISC-V core design, created as a joint effort between ETH… Read More

OpenPiton’s JuxtaPiton Processor to get Open-Source i486 Core

Kunal Gulati, working with the OpenPiton Project’s Jonathan Balkind and Katie Lim under the Free and Open Source Silicon Foundation (FOSSi) Google Summer of Code, has announced a project to expand the JuxtaPiton heterogeneous research processor with a third core: ao486. Announced back in November 2018, JuxtaPiton is the… Read More

Shakti RISC-V Processor Project Releases Public Software Development Kit

The Shakti Processor Project, which has produced India’s first natively-manufactured processor, has publicly released the Shakti Software Development Kit (SDK) – meaning application development for the RISC-V based chips can now begin. Featured in one of AB Open’s Open Source Digital Design Insights (OSDDI) interviews, the Shakti Processor Project… Read More

Embench Embedded Benchmark Project Calls for Aid

A call-to-arms has been raised by the Embench team for assistance in developing a new, fully-open benchmark suite designed to offer embedded developers an alternative to the products of the Embedded Microprocessor Benchmark Consortium (EMBC). As detailed in an article on EE Times, the Embench team is working to… Read More

Antmicro Launches Renode 1.7 with TSN, PTP Support, PicoRV32, Murax SoC

Antmicro has announced the release of Renode 1.7 – quickly followed by version 1.7.1 – with the framework’s first support for time-sensitive networking (TSN) and precision time protocol (PTP) on RISC-V platforms. An open-source simulation framework popular among those working within the proprietary Arm and open RISC-V ecosystems, and recently… Read More

Building a RISC-V PC

How we assembled a RISC-V desktop computer. (video at the bottom of this post.) While it’s clear that the most significant opportunities for RISC-V will be in democratising custom silicon for accelerating specific tasks and enabling new applications — and it’s already driving a renaissance in novel computer architectures, for… Read More