Tag: FOSSi

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

CRU: RISC-V Security, GraphQL Foundation, lowRISC 0.6, and More

Esperanto Technologies, a company focused on developing energy-efficient many-core accelerators for artificial intelligence and machine learning applications, has announced the closure of a whopping $58 million in Series B funding – more than 10 times its previous investment rounds combined. “Despite still operating largely in stealth mode, we appreciate this… Read More

Sipeed Launches Crowdfunder for RISC-V MAIX AI Dev Boards

Chinese electronics company Sipeed has launched a crowdfunding campaign for a range of development boards based on a Kendryte K210 dual-core 64-bit RISC-V processor, aiming to bring artificial intelligence (AI) processing to edge devices and with pricing starting at $5 per board. “Sipeed MAIX is the first RV64 AI board… Read More

lowRISC 0.6 Release Brings Performance, Documentation, Ethernet Improvements

The lowRISC project has announced the release of version 0.6 of its open silicon offering, bringing improvements to performance, debugging, and network connectivity – alongside a pledge to add alternative RISC-V cores to the current Rocket option. Ten months after the release of lowRISC 0.5 brought initial support for… Read More

Hex Five, Andes, Gowin Collaborate on MultiZone Security Implementation

Hex Five Security, Andes Technology, and Gowin Semiconductor have jointly announced a collaboration which will see the former’s trusted execution environment added to the middle’s N(X)25 RISC-V cores on the latter’s GW-2A field programmable gate array (FPGA) family. “The cost of a robust security implementation on RISC-V is now negligible… Read More

RISC-V AI Accelerator Specialist Esperanto Closes $58m Funding Round

CRU: RISC-V Grows Apace, RTOS Vulnerabilities Patched, and More

The IIT Madras SHAKTI Project has celebrated a major milestone this month: the first boot of a RISC-V processor both designed and manufactured within its native India. Launched in 2014 with a focus on IBM’s Power instruction set architecture (ISA) before switching to the open-source RISC-V ISA, the Shakti Project… Read More

SiFive Launches New E7, S7, U7 RISC-V Cores

RISC-V pioneer SiFive has announced a new family of processor cores, the Core IP 7 Series, which it claims are “the highest performance commercially available RISC-V cores” and which come in hard-real-time, performance, and Linux-capable variants. “The SiFive Core IP 7 Series represents a major advancement in RISC-V. The 7… Read More

SHAKTI Project Team, Courtesy of Silicon India

SHAKTI Project Boots Linux on Home-Grown 180nm RISC-V Silicon

S3 Semi’s Edel Griffith Busts Custom Silicon Myths

S3 Semiconductors’ Edel Griffith has published a piece on Electronic Design busting 11 myths about custom silicon, from production of application-specific integrated circuits (ASICs) being too expensive for lower-volume projects and fear of a so-called “black-box design” process. Designed to encourage companies to look more closely at custom… Read More

CRU: RISC-V Design Contest, Radio Spectrum Harmisation, Mbed Linux, and More

The RISC-V Foundation has announced the launch of a design contest, in partnership with Google, Antmicro, and Microchip, which will see entrants competing to build the smallest and fastest RISC-V soft core implementations on field-programmable gate arrays (FPGAs). One of the biggest benefits of free and open source silicon (FOSSi)… Read More

Clifford Wolf launches Yosys Open Synthesis Suite 0.8

Developer Clifford Wolf has announced the release of Yosys 0.8, the latest version of the popular open synthesis suite framework, bringing with it a range of new improvements and bug fixes. Designed to ease register-transfer level (RTL) development, analysis, and formal verification for projects written in the Verilog hardware description… Read More

Microsemi CreativeBoard FPGA development board