Hex Five Security, Andes Technology, and Gowin Semiconductor have jointly announced a collaboration which will see the former’s trusted execution environment added to the middle’s N(X)25 RISC-V cores on the latter’s GW-2A field programmable gate array (FPGA) family.
“The cost of a robust security implementation on RISC-V is now negligible – the future of RISC-V is security by default,” claims Don Barnetson, co-founder of Hex Five Security, of the company’s MultiZone Security which it has released as a free and open standard. “We’re very excited to enter the Chinese market with such strong partners and expand access to simple, robust security that any developer can implement.”
“The Chinese market will be the first mass adopter of RISC-V,” predicts Dr. Charlie Su, chief technology officer at Andes. “We’re happy to work with Hex Five to provide our customers a simple, robust security implementation that based on our RISC-V cores and comprehensive AndeSight, an Eclipse-based development environment and optimised toolchains to provide leading performance and reduced development time.”
“Increasingly, customers in China see security as a core requirement of their products,” adds Jim Gao, Gowin’s director of solution development. “With MultiZone Security, they can implement a robust security solution on our existing FPGAs without the need for new hardware, deep security expertise or even any changes to their toolset and workflow. This allows a customer to get to market fast, which is the goal of our FPGA solutions.”
The companies have confirmed that they will be demonstrating the MultiZone Security implementation at the Andes RISC-V Con on the 13th of November, while the standard itself is available to download now from GitHub.