The IIT Madras SHAKTI Project has celebrated a major milestone this month: the first boot of a RISC-V processor both designed and manufactured within its native India.
Launched in 2014 with a focus on IBM’s Power instruction set architecture (ISA) before switching to the open-source RISC-V ISA, the Shakti Project has already celebrated a number of breakthroughs: First-boot on its homebrew silicon occurred back in July this year, having been manufactured by US semiconductor giant Intel on a 22nm FinFET process node. Its latest achievement, though, speaks to its ultimate aim: the ability to produce chips locally, without any reliance on foreign nations.
As reported by Silicon India, the SHAKTI team has now booted a Linux-based operating system on one of its own RISC-V chips built entirely locally at the Indian Space Research Organisation (ISRO)’s Semiconductor Laboratory (SCL) in Chandigarh. While based on a considerably larger process node of 180nm to Intel’s 22nm, it represents a major breakthrough for India’s burgeoning semiconductor industry – and proof that the SHAKTI Project’s goal is achievable.
More information on the SHAKTI Project is available on the official website, while a video interview with Arjun Menon and Rahul Bodduna on the topic is available as part of AB Open’s Open Source Digital Design Insights (OSDDI) series.
RISC-V pioneer SiFive has announced a new family of processor cores, the Core IP 7 Series, which it claims are “the highest performance commercially available RISC-V cores” and which come in hard-real-time, performance, and Linux-capable variants.
“The SiFive Core IP 7 Series represents a major advancement in RISC-V. The 7 Series brings features to market that have been in-demand but unavailable to customers,” claims SiFive’s Jack Kang of his company’s latest launch. “SiFive offers the broadest portfolio of RISC-V Core IP with the most power efficient and highest performance cores. The 7 Series is our latest innovation that will allow designers to achieve higher efficiency by tailoring their core to the characteristics of their domain – from the smallest edge devices to the data center.”
The family starts with the E7 Core IP Series, a two-part 32-bit family with the single-core E76 and quad-core E76-MC both designed for use where hard-real-time operation is a requirement. The S7 Core IP Series is made up of the 64-bit single-core S76 and quad-core S76-MC, which target latency-sensitive applications including enterprise storage, storage compute, radio base stations and the like.
Finally, the 64-bit single-core U74 and four-plus-one-core U74-M4, which uses four U74 application cores and a single S7 monitor core, are designed to run full-featured operating systems including Linux – as the company’s previous U5 Series has proven on the HiFive Unleashed development board. The company has also pledged future variants with eight application cores.
Full details on the new cores, along with the company’s existing IP, can be found on SiFive’s Core Designer page.
S3 Semiconductors’ Edel Griffith has published a piece on Electronic Design busting 11 myths about custom silicon, from production of application-specific integrated circuits (ASICs) being too expensive for lower-volume projects and fear of a so-called “black-box design” process.
Designed to encourage companies to look more closely at custom and semi-custom silicon design, whereby application-specific parts are designed and produced to vastly improve efficiency over general purpose processors (GPPs) and other non-specific components in a variety of tasks, Edel’s piece argues that “recent changes in the semiconductor industry mean many of the preconceptions about custom chip design are no longer true,” pointing to ever-decreasing costs for fabrication as foundries look to use their capacities as efficiently as they can, the ability to run medium- and low-volume production, and a lowered barrier to entry for custom silicon design.
Edel’s piece busts 11 myths in total, but doesn’t quite cover the explosive change the semiconductor industry is currently experiencing: the rise of free and open source silicon (FOSSi), coupled with ultra-low-volume production options like OnChip’s Itsy-Chipsy service are not only making custom silicon available to smaller companies but even to individuals. Where it would once have required an up-front licensing fee in the tens or hundreds of thousands of dollars to pick up the core intellectual property (IP) behind a customised chip, ready-to-run core implementations are just a git-clone away for absolutely anyone to enjoy.
“Having custom SoCs [systems on chips] designed specifically for your application delivers an optimised solution in terms of power efficiency, performance, board space, and bill-of-materials (BOM) costs,” Edel explains. “Taking the custom approach also enables solutions with unique capabilities that would be difficult to achieve using off-the-shelf hardware, and it creates devices that are difficult to reverse-engineer, giving IP security.”
Edel’s full piece is available on Electronic Design now.
Security researcher Ori Karliner, of Zimperium’s zLabs, has warned of a range of vulnerabilities in the popular open-source FreeRTOS real-time operating system kernel – and with remote code execution possible, developers using the platform are urged to patch.
Made available under the MIT Licence, FreeRTOS supports a wide range of platforms and its small size combined with the provision of pre-written configurations and demonstrations for all supports ports and compilers has made it a popular choice for embedded developers. Sadly, that very popularity means that a selection of remote code execution vulnerabilities – which allow attackers to execute arbitrary code over a remote network connection – is of serious concern.
“During our research, we discovered multiple vulnerabilities within FreeRTOS’s TCP/IP stack and in the AWS secure connectivity modules. The same vulnerabilities are present in WHIS Connect TCP/IP component for OpenRTOS/SafeRTOS,” writes Ori Karliner of the security flaws. “These vulnerabilities allow an attacker to crash the device, leak information from the device’s memory, and remotely execute code on it, thus completely compromising it.”
Following the discovery of the vulnerabilities, Ori and colleagues at zLabs communicated details of the flaw to project maintainer Amazon which has now patched the issues in FreeRTOS version 1.3.2 and above. “Since this is an open source project,” Ori adds, “we will wait for 30 days before publishing technical details about our findings, to allow smaller vendors to patch the vulnerabilities.”
More information on the discovery is available on the Zimperium blog, along with an email address to contact the company if you believe you have shipped a product with a vulnerable version of FreeRTOS.
The OpenStack Foundation, in partnership with Wind River and Intel, has released a new open-source edge computing platform aimed at, among others, low-latency Internet of Things (IoT) applications: StarlingX.
“When it comes to edge, it is crucial to be able to blend together and manage all the virtual machine and container-based workloads and underlying bare metal environment,” claims OpenStack Foundation Jonathan Bryce of the project, which was founded back in May and has this week issued its first public release. “This is exactly what you get with StarlingX.”
“Intel is proud of our contributions to StarlingX and work to build a resilient cloud infrastructure for edge, industrial Internet of Things (IoT) and telecom applications,” adds Intel Open Source Technology Centre general manager Imad Sousou. “Today marks a major milestone with the release of the full StarlingX software package. Congratulations to everyone involved for delivering an open, distributed Edge solution that supports high-availability and ultra-low-latency.”
Among the use cases targeted by StarlingX are ultra-low-latency industrial IoT efforts including automation, cloud radio access network (RAN), and smart city metering and monitoring, along with multi-access edge computing efforts in the augmented and virtual reality (AR and VR) spaces, high-definition video content delivery, small cell service provision, and universal customer premise applications. The project has already attracted 84 contributors who have issued 1,329 commits to the codebase for its first release.
More information is available on the official website, while the source code – published under the Apache Licence Version 2.0, is available on the project’s Git repository.
Finally, TechInsights’ Jefferson Chua and Daniel Yang have published a comparative piece looking at the four main low-power wide-area networking (LPWAN) technologies currently vying for the Internet of Things (IoT): LoRa, Sigfox, NB-IoT, and LTE-M.
In the piece, published on Electronic Design, the pair compare the four primary LPWAN standards currently available, along with a look at five complementary short-range wireless standards, in a novel manner: as well as looking at their specifications, including power requirements, frequencies used, and data rates, the analysis extends to high-quality photographs of transceiver dies – offering a means of comparing the hardware used for each standard in a way not normally available outside each companies’ respective design labs.
“The explosion of the IoT market has resulted in a new type of network technology – LPWAN – that supports the long-range communications, low power usage, and affordability required by IoT standards guidance and industry use,” the pair explain by way of introduction. “We have examined the four main LPWAN technologies from the reverse-engineering angle by means of semiconductor die analysis. Each technology has its advantages and will continue to have its place in the IoT market. We believe that the LPWAN market will grow very quickly in the near future, and we look forward to seeing its impact on IoT technology.”
The full article, with high-quality die shots for all four major LPWAN standards, can be found over on Electronic Design now.