Tag: FOSS

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

SiFive HiFive1 Board, Courtesy of SiFive

CRU: RISC-V’s Bumper Year, LoRaWAN Growth, cocotb 1.1, and More

The RISC-V Foundation has released a video highlighting some of the key features of the 2018 RISC-V Summit, held in Santa Clara late last year and attended by over 1,100 community members. To say that the free and open source silicon (FOSSi) movement in general and RISC-V in particular had… Read More

The Kronos Group Calls for Comments on Heterogeneous Communications Standard

The Khronos Group, best known for its work on the OpenGL and OpenCL graphics and compute language standards, has called for feedback on the potential formation of a working group targeting a new low-level, heterogeneous communications standard for high-performance embedded computing (HPEC). Targeting markets ranging from the Internet of Things… Read More

CRU: Raspberry Pi Goes RISC-V, New FOSS Business Model, KiCon 2019, and More

Wave Computing has announced the MIPS Open initiative, under which it plans to make the instruction set architecture (ISA) available free of charge with no licensing or royalty payments required – a clear response to the growing popularity of the open RISC-V ISA. Wave Computing, which acquired MIPS from Imagination… Read More

Design News Picks 2019 as “The Year of Open Source”

Design News’ Chris Wiltz has predicted that 2019 will be “the year of open source,” and while it’s hard to imagine the impact of open source software getting any greater than it already has it’s clear that the impetus behind open hardware is growing at an exponential pace. In the… Read More

Tidelift Promises a “Better Business Model” for Open Source

Tidelift, a company founded by former Red Hat staff which aims to provide sustainable funding to open source projects, has announced a $25 million Series B funding round – on top of $15 million it raised last year. “Tidelift makes it possible for open source creators to get paid for… Read More

KiCon 2019 Launches as First KiCad User Conference

The KiCad community is to get its first-ever dedicated conference this year, in the form of KiCon 2019 which is to be held this April in Chicago, USA. Designed to bring together both users and developers of the open-source KiCad electronic design automation (EDA) software suite, KiCon 2019 has been… Read More

VerilogCreator Tunes QtCreator IDE for FPGA Project Use

Engineers working on field-programmable gate array (FPGA) projects and looking for a friendly development environment to add to their toolchain now have a new option: the VerilogCreator plugin for QtCreator. Written by Rochus Keller and brought to our attention by Hackaday, VerilogCreator is designed to turn the QtCreator integrated… Read More

CRU: Free RISC-V Boards, Security in the FOSSi Era, and More

OpenISA has officially launched the VEGAboard microcontroller development board, based on the PULP Platform’s RI5CY and Zero-RI5CY RISC-V core, and it’s giving them away to encourage adoption of the free instruction set architecture (ISA). Developed in partnership with the Parallel Ultra Low Power (PULP) Platform, Express Logic, Foundries.io, Ashling, IAR… Read More

Joint Development Foundation Joins Linux Foundation for Easier Standardisation

The Linux Foundation has announced that it is bringing the Joint Development Foundation under its wing, in order to bring together open source and open standards development and simplify the route to standardisation for developers. The partnership between the two organisations will, they claim, benefit both individual open-source developers and… Read More

Tom Verbeure on the VexRiscV CPU: “A New Way to Design”

Engineer Tom Verbeure has written up an analysis of the VexRiscV CPU, a RISC-V design implemented using the novel SpinalHDL hardware description language (HDL) – an approach he describes as being “as efficient as the most optimised Verilog, yet at the same time extremely configurable.” First-prize winner in the recent… Read More

Western Digital Unveils Open SweRV RISC-V Core

Western Digital has unveiled its first in-house RISC-V core, dubbed SweRV, and it has confirmed plans to release it under an open source licence early next year. Part of a company initiative, started in 2017, to switch from proprietary instruction set architectures (ISAs) to the open RISC-V ISA across its… Read More

CRU: RISC-V Growth, Transprecision Funding, Reverse-Engineering, and More

Princeton University’s OpenPiton free and open source silicon (FOSSi) project has announced what is claimed to be the world’s first open-source, general-purpose, heterogeneous-ISA processor: JuxtaPiton. Built by combining the SPARC v9-based OpenPiton with Clifford Wolf’s PicoRV32 RISC-V core, JuxtaPiton is something unique. “JuxtaPiton inherits all of the capabilities of OpenPiton,… Read More