Princeton University’s OpenPiton free and open source silicon (FOSSi) project has announced what is claimed to be the world’s first open-source, general-purpose, heterogeneous-ISA processor: JuxtaPiton.

Built by combining the SPARC v9-based OpenPiton with Clifford Wolf’s PicoRV32 RISC-V core, JuxtaPiton is something unique. “JuxtaPiton inherits all of the capabilities of OpenPiton, with the added ability to instantiate chosen tiles with RISC-V cores, rather than the usual OpenSPARC T1 core, which uses the SPARC v9 ISA,” OpenPiton’s Jonathan Balkind explains. “When implemented on FPGA, JuxtaPiton can boot Debian Linux on an OpenSPARC core as with OpenPiton. With the addition of a PicoRV32 core in the system, the OpenSPARC core can offload the execution of RISC-V binaries to be natively executed on the PicoRV32 core. When the RISC-V binary needs to make a system call, it can proxy it on the OpenSPARC core instead.”

The new JuxtaPiton RISC-V capabilities form part of OpenPiton v9, released earlier this week. As with all releases, downloads are available both from the OpenPiton website and the project’s GitHub repository.

The work on JuxtaPiton, which is understood to be the first open-source general-purpose processor design to include heterogeneous instruction set architecture (ISA) capabilities, is to be presented at the FPGA 2019 conference by lead author Katie Lim. Her paper, written with Jonathan Balkind and David Wentzlaff, is available now via uder the title “JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores.”

The RISC-V Foundation and the Linux Foundation have announced a joint initiative which they claim will “enable a new era of open architecture” and “accelerate open source development and adoption of the RISC-V ISA [Instruction Set Architecture].”

“With the rapid international adoption of the RISC-V ISA, we need increased scale and resources to support the explosive growth of the RISC-V ecosystem. The Linux Foundation is an ideal partner given the open source nature of both organisations,” explains Rick O’Connor, executive director of the non-profit RISC-V Foundation’s decision to partner with the Linux Foundation. “This joint collaboration with the Linux Foundation will enable the RISC-V Foundation to offer more robust support and educational tools for the active RISC-V community, and enable operating systems, hardware implementations and development tools to scale faster.”

“RISC-V has great early traction in a number of markets with applications for AI [Artificial Intelligence], machine learning, IoT [Internet of Things], augmented reality, cloud, data centres, semiconductors, networking and more. RISC-V is a technology that has the potential to greatly advance open hardware architecture,” adds Jim Zemlin, executive director at the Linux Foundation. “We look forward to collaborating with the RISC-V Foundation to advance RISC-V ISA adoption and build a strong ecosystem globally.”

The partnership will see the Linux Foundation providing neutral governance and best practices for open source development alongside resources including but not limited to training programmes, infrastructure tools, community outreach, marketing, and legal expertise.

The two organisations are already collaborating on the first of these resources, a pair of “getting started” guides for the open-source RISC-V-compatible Zephyr real-time operating system (RTOS) which will be formally unveiled during the RISC-V Summit event on the 3rd of December.

Thales Group, best known for its work in aerospace, defence, transportation, and security, has announced it has joined the RISC-V Foundation, declaring its commitment to “free, open-source hardware architectures based on RISC-V processors.”

Founded in 2000 as the next stage from 1968-founded Thomson-CSF, which in turn was an evolution of Compagnie Française Thomson-Houston (CFTH) founded in 1893, Thales’ primary work is in high-security markets. That security focus, the company has announced, is now being brought to bear on the RISC-V open instruction set architecture (ISA) – with the company positioning itself to “play a major role in a new era of microprocessor design.”

“The success of open source hinges on community engagement, and Thales is a dedicated member of the community,” claims Thales’ chief technology officer Marko Erman. “Joining the RISC-V Foundation underscores the Group’s commitment to a coordinated approach by industry and academia to the design of secure, dependable microprocessors.”

The company’s primary goal, it says, is to enhance the security and dependability of Internet of Things (IoT) devices, embedded systems, and machine learning implementations, and it is looking to work with existing companies in the field to establish security best-practices for hardware development. The company’s announcement further praises the work done in the field by RISC-V, saying it has “made significant inroads in recent years in the effort to protect microprocessors from cyber threats” and that the company plans to work with open source communities to design processors compatible with the needs of future critical systems.

“By adopting an open approach to both hardware and software,” the company’s announcement concludes, “Thales and the RISC-V community are opening up new opportunities for the design of mission-critical systems in all sectors, including aerospace, space, automotive, rail transport, security and defence.”

Frank Gurkaynak, director of the Microelectronics Design Centre at ETZ Zürich, has announced a 2019 “summer of code” programme that will see a selection of open-source project proposals granted up to €6,000 in funding as part of the Open Transprecision Computing (PRECOMP) project.

“First of all, what is Transprecision computing? It is all about using the right precision for computing and adapt the numeric precision (and the associated memory and computation energy overhead) throughout the computation to the requirements of the application,” Frank explains. “The idea is similar to approximate computing (trading off accuracy with performance), but also considers where the precision is adapted throughout the operation. As a simple example consider iterative algorithms that try to minimize the error with each iteration. The longer you iterate the smaller your error will become. So you can start your computations with coarser representations (i.e. half precision floating point) and move to higher precision formats (i.e. double precision floating point) as the computation progresses. Our goal is to find cases where working in this way can gain significant savings without noticeable loss in accuracy.

“In our 3rd year of the project, we would now also like to enlist the help of students, professionals and enthusiasts through a sponsored ‘summer of code’ activity. The idea is simple, send us your ideas on what you want to do with transprecision computing until 1st of March 2019. The applications will be reviewed and we will support at least 10 projects with €4,000 to €6,000 and announce them by 1st of May. We will have a kick-off meeting as part of the Week of Open Source Hardware (WOSH) that we are planning between 11th and 14th of June 2019 in Zurich, and we will provide an opportunity to all participants to take part and present their results at the Oprecomp Summer School which will take place in early September in Perugia, Italy.”

OPRECOMP has named a variety of potential project topics, including software, kernels, and algorithms implemented on existing hardware systems, the creation of novel hardware systems implemented on field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), and applications ported to OPRECOMP member platforms. The programme is open to members of the European Union, and accepted projects must be made widely available using an open source licence.

More information, and a a form for applicants, can be found on the official website.

Microelectronics industry standards organisation JEDEC has announced that it plans to release 3D models of new standard modules, packages, and socket outlines, in addition to the traditional 2D drawings it provides.

“The demand for 3D models in electronics design and manufacturing is set to grow exponentially with the expansion of the Internet of Things and the drive towards digital manufacturing through automation,” claims John Norton, chair of the JEDEC JC-11 Mechanical Standardisation Committee. “JEDEC is helping to enable this growth through the development of 3D models for our standard designs to complement the 2D drawings offered today and by establishing a universal schema for presenting real part data to software. These resources will greatly reduce time to market, eliminate opportunities for human error, and reduce manufacturing costs across the industry.”

The organisation has confirmed that the parts will be made available in a standard, universal format which can be imported by the most common 3D computer aided design (CAD) packages in use in the microelectronics industry today. It has also announced a new standard schema based on the Extensible Markup Language (XML), which will allow for the automatic generation of compatible 3D models based on user inputs or information stored in a database.

The models are not yet available, but more information is set to be published to the JC-11 Mechanical Standardisation committee page in the near future.

Finally, reverse engineering is often a high-tech, expensive endeavour – but David Freitag’s latest project takes it down to the bare essentials, attacking a USB 3.0 eMMC reader board with nothing more than a desoldering station, sandpaper, and a flatbed scanner.

“Say there’s a Chinese silicon vendor which designs and sells a chip that does a lot of really fancy stuff. You’re super interested because said fancy bits can be had for the low low price of a few hundred pennies. Awesome, you might say, lets buy them! But there’s an issue,” David explains of the reason for his needing to reverse engineer a four-layer printed circuit board. “Documentation. Silicon vendors, Chinese or otherwise, have a nasty habit of making it nearly impossible to find proper documentation for a specific product; whether it’s poorly documented, NDA’d, or in some cases simply nonexistent.”

While the obvious fix would be for vendors to improve their documentation, possibly even to make their development hardware and reference designs available under an open source hardware licence, David’s approach requires no cooperation from the vendor – but it does require a certain amount of care, a lot of patience, and a steady hand with 600-grit sandpaper.

“You’re going to need some hot air reworking tools and a relatively high DPI scanner,” David explains, showing how the hot-air station can be used to remove larger components and the scanner to take high-resolution imagery of the two exposed layers of the PCB. The sandpaper, then, comes in handy to remove first the soldermask and then the upper layers of the PCB to expose the two hidden, inner layers and their traces.

“Once you have exposed layer 3 (which in this case was frustratingly only solid ground pour), take all of your scans and composite them,” David continues, showcasing how the scans can be combined into an image which makes clear which layer each trace belongs to and where it goes. “Set each layer to a pure colour by dumping the saturation and tweaking with the layer opacity until you get something you can understand.”

The full process, along with the in-progress and final images and links to David’s work-in-progress schematic and Eagle library, can be found on