Tag: FOSS

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

VSDOpen 2019 Online Conference Scheduled for Saturday 19th October

VLSI System Design (VSD) has announced VSDOpen 2019, its second annual online conference for the semiconductor industry – with a focus on open-source electronics design automation (EDA) and the RISC-V instruction set architecture. Following the success of VSDOpen 2018, VLSI System Design has scheduled its second annual online conference –… Read More

CHIPS Alliance Announces Two-Day Open-Source Design Verification Workshop

CHIPS Alliance has opened registration for a two-day open-source design verification workshop, taking place on the 14th and 15th of November in Munich, Germany. Launched back in March, CHIPS Alliance is a Linux Foundation project focused on supporting the burgeoning free and open source silicon (FOSSi) movement. Its first… Read More

CRU: New Open Silicon Releases, Xilinx’ Vitis, and More

Semiconductor Engineering’s Ann Steffora Mutschler has highlighted the growing popularity of open instruction set architectures (ISAs) like RISC-V and the newly-opened Power ISA, in a piece with input from a range of industry experts. “It’s become so cumbersome to go into building chips because of all these factors,” OpenPOWER processor… Read More

Xilinx Turns to Open Source for New Vitis Unified Software Platform

Xilinx has announced the launch of the Vitis development platform, designed to allow the like of software engineers and artificial intelligence (AI) scientists to take advantage of field-programmable gate arrays (FPGAs) – and it builds on open-source software. “With exponentially increasing compute needs, engineers and scientists are often limited by… Read More

1st CLaaS and Google Summer of Code Work to “Open The Floodgates” of Free and Open Source Silicon

Redwood EDA’s Steve Hoover has written of a Google Summer of Code student who “helped open the floodgates” of free and open source silicon (FOSSi) by contributing to the 1st CLaaS framework project: Ákos Hadnagy. “While [the] open source silicon community is a hotbed of enthusiasm, it is several decades… Read More

CRU: RISC-V Momentum, Carbon Nanotubes, Fire, ICE, and More

RISC-V Foundation chief executive officer Calista Redmond has written of increasing momentum for RISC-V, as the semiconductor industry begins to shift away from proprietary closed-source core. “Interest in RISC-V has been gaining steam with commercial implementations and adoption rapidly growing. It has been incredible to witness how RISC-V has fostered… Read More

Linux 5.3 Released After Extra RC, Brings Numerous RISC-V Improvements

Linus Torvalds has officially launched Linux 5.3, the latest release of the popular open-source kernel, and it brings with it a range of improvements and new features for the RISC-V instruction set architecture (ISA). “So we’ve had a fairly quiet last week, but I think it was good that we… Read More

FOSSi Foundation Details Google Summer of Code 2019 Project Wins

The Free and Open Source Silicon (FOSSi) Foundation has announced the end of its participation in the 2019 Google Summer of Code programme, with seven students contributing to projects under the Foundation’s umbrella mentorship. Run by Google each year as a means of matching students with mentors already in the… Read More

CRU: LoRaWAN World Records, SweRVolf SoC, OpenPower, and More

The Things Network, the community-driven LoRaWAN project, has announced a world record successful transmission distance from the Servet project: 476 miles, or 766 kilometres. Designed for low power yet wide area use, LoRaWAN is the technology behind community-driven wide-area networking project The Things Network – the largest open LoRaWAN network… Read More

QEMU 4.1.0 Extends RISC-V Open ISA Support

The open-source QEMU machine emulator and virtualiser has received enhanced support for the open RISC-V instruction set architecture (ISA) in its 4.1.0 release. Following on from the 4.0.0 release back in April, QEMU 4.1.0 brings a range of improvements to its support for the open RISC-V ISA. Chief among… Read More

CHIPS Alliance Launches FuseSoC-Based SweRVolf System on Chip Design

CHIPS Alliance has launched a system-on-chip (SoC), built using Western Digital’s open-source SweRV Core and the FuseSoC build toolset, dubbed SweRVolf A collaboration between FuseSoC creator and maintainer Olof Kindgren, Western Digital Director of Next Gen Platforms Tech Zvonimir Bandic, outgoing chief technology officer Martin Fink, and CHIPS Alliance, SweRVolf… Read More

FSFE Launches REUSE 3.0 Licence Compliance Specification, Support Tool

The Free Software Foundation Europe (FSFE) has announced the release of REUSE 3.0, a copyright and licensing specification and supporting utility designed to make license compliance as simple as possible for free and open source projects. “The licensing of a software project is critical information,” explains FSFE’s Carmen Bianca Bakker… Read More