Semiconductor Engineering’s Ann Steffora Mutschler has highlighted the growing popularity of open instruction set architectures (ISAs) like RISC-V and the newly-opened Power ISA, in a piece with input from a range of industry experts.
“It’s become so cumbersome to go into building chips because of all these factors,” OpenPOWER processor enablement director Mendy Furmanek tells Mutschler, referring to the complexity of entering into multiple agreements with multiple intellectual property holders. “At the same time, we really need the innovation. That’s why this [open ISA] movement is happening rapidly. We’ve got to get all of these barriers out of our way. It’s not just about money. It’s about all those things. But ultimately, it’s about faster innovation.”
“Ecosystems are fundamentally about efficiency,” adds Imperas Software chief executive Simon Davidmann. “As a processor core becomes popular, the growing pool of developers and projects attracts ecosystem investment to develop tools and solutions to help them. This becomes a snowball effect as popularity drives more adoption and attracts more solutions across wider areas of requirements. Ultimately the value and efforts extended by the ecosystem can be a many-fold. The key is software reuse.
“But it’s a symbiotic relationship. Innovation on the processor needs to evolve and include support from the ecosystem. This cannot be forced. There are many examples of hardware innovation that failed to gain the critical mass of ecosystem support or migrate successes in one market segment to another. An open ISA has the one advantage over traditional IP approaches in that, while it may not have a roadmap in detail pre-defined, it has a structure that permits optimization and customization. If the ecosystem can fully support this inherent flexibility, any new hardware should see less barriers to future adoption.”
There is one clear dissenting voice in the piece, it must be said: Arm vice-president Tim Whitfield, who has seen the growth of open ISAs in general and RISC-V in particular chipping away at his company’s majority share of the embedded market. Whitfield’s comments echo those used in an ill-judged and quickly-removed anti-RISC-V marketing campaign launched by Arm back in 2018.
Mutschler’s full piece is available over on Semiconductor Engineering now.
High-performance computing (HPC) specialist Inspur has announced the release of TF2, a full-stack framework for efficient artificial intelligence computing on field-programmable gate arrays (FPGAs), under the permissive Apache 2.0 licence.
“The deployment of AI applications covers the cloud, the edge, and the mobile end, and has highly diverse requirements. TF2 can greatly improve the efficiency of application deployment across different ends and quickly adapt to the model inference requirements in different scenarios,” says Liu Jun, general manager for artificial intelligence and high-performance computing at Inspur Group. “AI users and developers are welcome to join the TF2 open-source community to jointly accelerate the deployment of AI applications and facilitate the implementation of more AI applications.”
The release covers both halves of the TF2 framework: the first half is a model optimisation and conversion tool for compression, pruning, and quantisation of network model data from common deep-learning frameworks; the second is a runtime engine which converts optimised model files into FPGA target running files with improved performance and efficiency – up to 12.8 times the speed of a more general implementation on the same hardware, using the FaceNet model. The project also includes a software-defined reconfigurable chip design architecture, designed to support the development of current convolutional neural network (CNN) models while supporting easy porting for the development of other network models including Transformer and LSTM.
As well as releasing the project under the permissive Apache 2.0 licence, Inspur has confirmed it plans to continue to invest in establishing an open-source community surrounding TF2 with efforts including new automatic model analysis, structural pruning, sparse computing, and other additional features to follow in the coming months. Inspur has named Kuaishou, Shanghai University, and MGI as early members of the community.
The TF2 framework is available now on GitHub, along with supporting documentation.
Redwood EDA’s Steve Hoover has written of a Google Summer of Code student who “helped open the floodgates” of free and open source silicon (FOSSi) by contributing to the 1st CLaaS framework project: Ákos Hadnagy.
“While [the] open source silicon community is a hotbed of enthusiasm, it is several decades behind the world of open source software,” Hoover writes, listing “three reasons this movement has, thus far, not been able to take off like open source software” and “why these three obstacles are all coming to a very sudden and dramatic end, that will unleash a tidal wave, catching the silicon industry by surprise.
“So, why is coding and sharing circuit models any different from sharing software? Three reasons: implementation details; access to software, access to hardware,” Hoover explains. “My personal contributions to this open source silicon movement stem from my startup, Redwood EDA. We directly target problem #1 by providing tools that support advanced (yet simpler) circuit modelling techniques. And, to address #2, we make all of our software freely available online for open source development. But neither open source EDA nor the efforts of my startup had been able to noticeably impact problem #3, access to hardware.
“In the past few years, cloud providers have begun incorporating FPGAs into their datacentres. These are available to anyone with an internet connection and a credit card, bundled with industry-class EDA software, on a pay-per-use basis. Wow! This is the solution to hardware access! An open source developer can provide not only their hardware model but also the platform for which their model was designed. A user can download and go, just like they can with software! …in theory. So here’s the rub. The learning curve for cloud FPGA platforms has been way too high for the open source community to latch on.”
Returning Google Summer of Code participant Hadnagy worked with Hoover to build up an FPGA webserver framework dubbed “1st CLaaS” – custom logic as a service. “Very simply, 1st CLaaS wraps a developer’s custom FPGA logic as a microservice. Standard web protocols can be used to stream bits to and from this logic, and platform details are hidden by the framework,’ Hoover explains. “So there is no longer anything standing in the way! Hobbyists can build and share hardware, and open source silicon can thrive. Just imagine the disruption this will have on the industry, which is currently driven by corporate giants. And with easy web integration, the opportunity and demand for hardware acceleration should rise, and we could start to see some interesting new capabilities on the web that were not imaginable until now.”
Hoover’s full post is available on the Google Open Source blog, while 1st CLaaS is available on GitHub under the BSD 3-Clause licence. Hadnagy, meanwhile, presented on the project at the recent ORConf free and open source silicon conference.
The RISC-V Foundation has announced the winners of its RISC-V Soft CPU Contest, launched back in July with a view to promoting security-focused RISC-V implementations.
“With the proliferation of connected devices, security is one of the key challenges in hardware design. The free and open RISC-V ISA presents an incredible opportunity for the ecosystem to collaborate to develop more robust solutions for the growing security demands of today and the future,” said RISC-V Foundation chief executive Calista Redmond at the opening of the contest. “This contest is an opportunity for designers and hardware enthusiasts to rethink what is possible with computing design and build a secure RISC-V soft CPU that can prevent software security attacks.”
Now, the Foundation has announced the winners – and taking the top prize of €5,000 plus a HiFive Unleashed with Expansion Board add-on is Changyi Gu, whose Rattlesnake soft core scored 78 out of a possible 100 on the judging metrics while implementing a “dirty bit” protective system to tag consecutive suspicious writes and halts if tagged memory is executed.
The second-place prize went to Matthew Ballance for Featherweight RISC-V (FWRISC-S), which protects defined memory areas until the core is reset. Finally, third place went to Jörg Mische for RudolV, which also allows for memory regions to be defined as non-executable when associated with suspicious memory writes.
A special mention was also given to Ecco, a team made up of Alexey Baturo, Anatoly Parshintsev, Fedor Veselovsky, Igor Chervatyuk and Sergey Matveev, who presented a soft-core processor which implements memory tagging using a pseudorandom number generation. “Starting from the SPU32 processor, they showcased how RISC-V can enable anyone to work at a hardware level, even a team made up of software engineers,” the Foundation explains. “While the Ecco team’s solution ran on a different board than outlined by the contest rules (and was thus ineligible to win), we appreciate all their hard work.”
Xilinx has announced the launch of the Vitis development platform, designed to allow the like of software engineers and artificial intelligence (AI) scientists to take advantage of field-programmable gate arrays (FPGAs) – and it builds on open-source software.
“With exponentially increasing compute needs, engineers and scientists are often limited by the fixed nature of silicon,” claims Victor Peng, president and chief executive officer of Xilinx. “Xilinx has created a singular environment that enables programmers and engineers from all disciplines to co-develop and optimize both their hardware and software, using the tools and frameworks they already know and understand. This means that they can adapt their hardware architecture to their application without the need for new silicon.”
Based on a stack architecture, Vitis starts with a target platform featuring a board and preprogrammed input/output (IO); this is followed by the Vitis Core Development Kit, which is made up of the Xilinx open-source runtime library and development tools including compilers, analysers, and debuggers; the third layer is made up of eight libraries with more than 400 open-source applications, all of which are accelerated on the FPGA and can be called via a standard application programming interface (API).
The Vitis platform also includes Vitis AI, a domain-specific architecture (DSA) which configures Xilinx’ hardware for use with frameworks including TensorFlow and Caffe while providing APIs for deployment from edge to cloud; it will be followed by Vitis Video, which allows encoding directly from FFmpeg.
While Xilinx positions the Vitis platform as an alternative to ‘imposing a proprietary development environment‘ and promises to provide its libraries under open-source terms, the company has not indicated the platform itself will be released as such; instead, it promises to make it “free for [use with] Xilinx boards” next month. More information is available on the official website.
Finally, Wireless Broadband Alliance (WBA) and LoRa Alliance have announced the result of an investigative partnership looking into how Internet of Things (IoT) networks can benefit from a combination of Wi-Fi and LoRaWAN connectivity.
The two organisations, both of which champion differing network technologies in unlicensed spectra, collaborated on a white paper which found that a combination of Wi-Fi and LoRaWan – the former excellent for high-speed communication over short to medium distances, the latter specialising in low-power transmission over short, medium, or long ranges – proved promising for deployments including smart building, residential connectivity, and automotive projects.
“Wi-Fi and LoRaWAN are two important technologies utilising the unlicensed spectrum, and they already address a large proportion of IoT use cases,” explains Tiago Rodrigues, general manager of WBA. “The Deployment Synergies paper highlights the ways in which these technologies are impacting private-public business models and enabling IoT services, while also identifying ways in which the technologies complement one another and can be used to further expand the Internet of Things.”
“The reality is that no one single technology is going to fit the billions of IoT use cases,” adds Donna Moore, chief executive and chair of LoRa Alliance. “It is collaborative initiatives like this one with Wi-Fi that will drive innovation to solve important issues, leverage an even broader range of applications and, ultimately, ensure the success of global mass IoT deployments in the future.”
The white paper is available for immediate download from the LoRa Alliance website.