News

The latest on developments at AB Open and across the wider community.

OpenROAD Project Accepting Nominations for Open-Source Community Contribution Awards

The OpenROAD project, the University of California at San Diego’s initiative to reduce the cost, expertise, and risk barriers to hardware design through open-source, has opened nominations for Open-Source Community Contribution Awards. “The OpenROAD project is pleased to announce the establishment of its Open-Source Community Contribution Awards,” the organisation explains… Read More

CRU: Digital FOSSils, RISC-V Growth, Embench Benchmark, and More

AB Open’s Open Source Digital Design Insights (OSDDI) series has expanded with the launch of its first long-form article: Digital FOSSils, a look at the storied history of the free and open-source silicon movement. Today, while the term “free and open source silicon” might not be heard around every water… Read More

Semi Engineering Highlights Growing Industry Interest in Open-Source EDA

Semiconductor Engineering’s Kevin Fogarty has penned a piece on the industry’s increasing interest in open-source electronic design automation (EDA) tools, thanks in no small part to the growth of open hardware projects including RISC-V. “Open-source EDA is back on the semiconductor industry’s agenda, spurred by growing interest in open-source hardware,”… Read More

Digital FOSSils: A History of Free and Open Source Silicon

Today, while the term “free and open source silicon” might not be heard around every water cooler, it’s certainly becoming more common. Projects like RISC-V, which aim to create instruction set architectures which can be used in processors from ultra-low-power microcontrollers all the way up to many-core high-performance computing products,… Read More

Western Digital Partners with SiFive, PlatformIO for Extended Open-Source Dev Toolset

Western Digital has announced a partnership with SiFive and PlatformIO Labs which will see the latter’s embedded development platform extended in order to provide a vendor-agnostic, end-to-end open environment with full RISC-V support. Western Digital’s interest in embedded development in general and the open RISC-V instruction set architecture (ISA) specifically… Read More

Work Continues on Debian Linux RISC-V Port, Documentation Efforts

The Debian Linux distribution’s Manuel Montezelo has written of the progress in porting the distribution to the 64-bit RISC-V architecture, boasting of around a 90 percent package compatibility milestone. Announced back in April 2018, the Debian Linux RISC-V port had a long road ahead of it. At launch, around… Read More

X-FAB, Efabless Announces RISC-V-Based Raven Mixed-Signal SoC

X-FAB Silicon Foundries and Efabless Corporation have announced the creation of a new mixed-signal system-on-chip (SoC) reference design boasting a RISC-V core: Raven. Designed, its creators claim, in just three months, the open-source mixed-signal Raven SoC was built using an open-source tool set put together by Efabless. Its PicoRV32 32-bit… Read More

Embench Embedded Benchmark Project Calls for Aid

A call-to-arms has been raised by the Embench team for assistance in developing a new, fully-open benchmark suite designed to offer embedded developers an alternative to the products of the Embedded Microprocessor Benchmark Consortium (EMBC). As detailed in an article on EE Times, the Embench team is working to… Read More

European Processor Initiative Delivers First Architectural Designs

The European Processor Initiative (EPI) has announced the delivery of its first architectural designs to the European Commission, marking the first steps in its efforts to create a made-in-Europe processor family for high-performance and automotive computing. Launched in December 2018, the European Processor Initiative boasts 26 industry partners – up… Read More

Antmicro Launches Renode 1.7 with TSN, PTP Support, PicoRV32, Murax SoC

Antmicro has announced the release of Renode 1.7 – quickly followed by version 1.7.1 – with the framework’s first support for time-sensitive networking (TSN) and precision time protocol (PTP) on RISC-V platforms. An open-source simulation framework popular among those working within the proprietary Arm and open RISC-V ecosystems, and recently… Read More

CRU: ‘Unhackable’ Chips, Grove AI HAT, RISC-V Drones, and More

Researchers from the University of Michigan have announced a new RISC-V processor design with a strong focus on security, using ‘churn’ to keep attackers from exploiting vulnerabilities. “Today’s approach of eliminating security bugs one by one is a losing game,” claims Todd Austin, professor of computer science and engineering at… Read More

Western Digital’s Zvonimir Bandić Offers an Intro to SweRV Core

Western Digital’s Zvonimir Bandić has published an introduction to the company’s open SweRV Core, which it has released to the public following its efforts to move to the RISC-V instruction set architecture (ISA) for its future storage processing products. Western Digital unveiled the SweRV Core late last year, making… Read More