AB Open’s Open Source Digital Design Insights (OSDDI) series has expanded with the launch of its first long-form article: Digital FOSSils, a look at the storied history of the free and open-source silicon movement.
Today, while the term “free and open source silicon” might not be heard around every water cooler, it’s certainly becoming more common. Projects like RISC-V, which aim to create instruction set architectures which can be used in processors from ultra-low-power microcontrollers all the way up to many-core high-performance computing products, have become big news – and big business – thanks to the fact that anyone is free to use, hack, create, experiment, and release products on them without paying a single penny in licensing or royalties.
The free and open source silicon (typically shortened to “FOSSi”) movement didn’t begin with RISC-V, however. It has a history stretching back considerably further than that, even as far as the early days of personal computing.
X-FAB Silicon Foundries and Efabless Corporation have announced the creation of a new mixed-signal system-on-chip (SoC) reference design boasting a RISC-V core: Raven.
Designed, its creators claim, in just three months, the open-source mixed-signal Raven SoC was built using an open-source tool set put together by Efabless. Its PicoRV32 32-bit RISC-V processing core runs at 100MHz in bench testing, with simulations suggesting its clock rate could be boosted to 150MHz. Wedded to Efabless’ open-source top-level design is proprietary analogue IP from X-FAB – which, the company points out, was also developed using an open-source design flow.
“The successful partnership with Efabless demonstrates X-FAB’s continued commitment to open-source semiconductor development,” claims X-FAB’s Ulrich Bretthauer. “Nearly 75 percent of Raven’s die area is covered by X-FAB standard library blocks and macros. Using these proven IP blocks increased the reliability of the Raven while minimising first-silicon risk.”
“This project would not have been possible without the support of X-FAB,” adds Mohamed Kassem, Efabless co-founder and chief technical officer, of the partnership. “They have been an early adopter of the Efabless open-innovation model and this project is the logical extension of our collaboration.”
The first Raven chips have been produced on X-FAB’s XH018 180nm six-metal process, which the company states meets automotive quality requirements. For those interested in its design, the Raven SoC is available on the Efabless Design Catalogue with no licence fee attached.
The Debian Linux distribution’s Manuel Montezelo has written of the progress in porting the distribution to the 64-bit RISC-V architecture, boasting of around a 90 percent package compatibility milestone.
Announced back in April 2018, the Debian Linux RISC-V port had a long road ahead of it. At launch, around 70 percent of the packages available in the Debian software repositories – which includes everything from core operating system software to third-party applications and even games – had been successfully built for the 64-bit ‘riscv64’ architecture. By mid-2018, that figure had risen to around 80 percent; now, Montezelo reveals, it’s at around 90 percent.
“Sometimes things look very quiet from outside even if the people on the backstage never stop working,” Montezelo explains in a blog post on the topic. “So this is an update on the status of this port before the release of buster, which should happen in a few weeks and which it will open the way for more changes that will benefit the port.
“There are people working on ports at all times, keeping things working behind the scenes, and that’s why from a high level view it seems that things ‘just work.’”
There is work still to be done, however, and not only in getting the last 10 percent of the packages built for the architecture. “Due to several reasons, among them the limited availability of hardware able to run this Debian port and the limited options to use bootloaders during all this time, the instructions to get Debian running on RISC-V are not the best, easiest, more elegant or very up to date,” Montezelo admits. “This is an area to improve in the next months.
“Additionally, it would be nice to have images publicly available and ready to use, for both Qemu and hardware available like the HiFive Unleashed (or others that might show up in time), but although there’s been some progress on that, it’s still not ready and available for end users.”
Full details of the port’s progress can be found in Montezelo’s blog post.
Western Digital has announced a partnership with SiFive and PlatformIO Labs which will see the latter’s embedded development platform extended in order to provide a vendor-agnostic, end-to-end open environment with full RISC-V support.
Western Digital’s interest in embedded development in general and the open RISC-V instruction set architecture (ISA) specifically isn’t new: the company has long offered data processing products, and in December 2018 unveiled its in-house SweRV Core RISC-V implementation – released to the public under a permissive licence in January this year. Its partnership with SiFive and PlatformIO, though, goes still further in opening up the development ecosystem to all comers.
“By teaming up with PlatformIO, we are bringing the entirety of its multi-architecture embedded design environment, including debug and trace, to the open-source community. With deep libraries and automated support already built-in, this will allow programmers to easily transition among development platforms, including RISC-V,” explains Martin Fink, chief technology officer at Western Digital. “The expanded openness of PlatformIO, along with our recent enhancements to our SweRV Core and OmniXtend cache-coherent fabric, further lowers the barrier for RISC-V development and expands the potential for innovation that will enable us to realise the benefits of bringing compute power closer to data.”
“By teaming up with Western Digital and SiFive, we are able to further our vision to not only further expand the openness of the PlatformIO’s professional embedded development environment, but extend the PlatformIO ecosystem,” adds Ivan Kravets, chief executive officer at PlatformIO. “The ‘zero-configuration’ Platform Plus tools eliminate many of the most time-intensive aspects of software design and are enabling, better, less buggy code. By making these open-source, PlatformIO is now a fully free and open environment for next-generation design, from semiconductors to processor to software.”
“We are pleased to partner with Western Digital and PlatformIO to bring the PlatformIO’s tools to the open-source community,” concludes Yunsup Lee, chief technology officer at RISC-V pioneer SiFive. “The list of supported hardware and software solutions and automated capabilities offer the potential to reduce the time-to-market of innovative purpose-built software applications for IoT, AI, machine learning, analytics and more. As SiFive continues to drive innovation and provide leadership in the RISC-V space, an investment like this is key to enabling the marketplace for those who want to enjoy the benefits of the innovative solutions provided by RISC-V.”
More details on PlatformIO are available on the official website.
The European Processor Initiative (EPI) has announced the delivery of its first architectural designs to the European Commission, marking the first steps in its efforts to create a made-in-Europe processor family for high-performance and automotive computing.
Launched in December 2018, the European Processor Initiative boasts 26 industry partners – up from 23 at foundation – and has three primary goals on its roadmap: the creation of a general-purpose processor (GPP) with a focus on high efficiency; an accelerator, which is being built around the open RISC-V instruction set architecture (ISA); and an automotive platform.
“[The] European Processor Initiative will deliver key technologies to the new European HPC strategic plan for an independent and innovative European high-performance computing and data ecosystem,” claims Jean-Marc Denis, EPI chair. “Energy efficient high-performance families of EPI processors will include most advanced general-purpose and accelerator cores that will deliver unprecedented processing capabilities, enabling EU researchers from academia and industry to most efficiently address global challenges. The business sustainability of the initiative is supported by carefully balanced target markets, with primary focus on exascale HPC/AI and automotive markets.”
“Acceleration is crucial to continued performance gains while reducing power consumption in computing. In EPI, the first accelerator will begin from RISC-V technology,” adds Professor Mateo Valero, director of the Barcelona Supercomputing Centre, “to deliver two unique vector and artificial intelligence accelerators for HPC and AI, since future supercomputers will be mostly heterogeneous; the second accelerator, based on Kalray’s IP, will lead the path to deterministic automotive computation. Both are offering a European solution to future global converged (HPC and AI) computing needs.”
The EPI roadmap sees the first generation platform, codenamed Rhea, launched in 2021 and based on a combination of Arm and RISC-V cores; the second-generation Cronos family follows in 2022/20223; a third-generation family, yet to be codenamed, is scheduled to follow in 2024.
More information is available on the official website.
Antmicro has announced the release of Renode 1.7 – quickly followed by version 1.7.1 – with the framework’s first support for time-sensitive networking (TSN) and precision time protocol (PTP) on RISC-V platforms.
An open-source simulation framework popular among those working within the proprietary Arm and open RISC-V ecosystems, and recently praised by Dover Microsystems for helping to significantly shorten the company’s design cycle, the latest release of Antmicro’s Renode brings with it support for new soft-core RISC-V implementations including PicoRV32 and the Murax SoC.
In addition, experimental support for time-sensitive networking (TSN) and precision-time protocol (PTP) has been added to the framework – previously available only as part of the Cadence GEM Ethernet controller, and added as part of Antmicro’s effort to implement TSN and PTP in Zephyr for the Microchip SAM E70.
The new release also brings a range of improvements including better execution determinism, boosted usability, and in the v1.7.1 follow-up release an added integration layer for Verilator which allows for Verilog implementations to be used within a Renode simulation.
Finally, a call-to-arms has been raised by the Embench team for assistance in developing a new, fully-open benchmark suite designed to offer embedded developers an alternative to the products of the Embedded Microprocessor Benchmark Consortium (EMBC).
As detailed in an article on EE Times, the Embench team is working to produce an open-source benchmark for embedded developers which distils performance metrics from around 20 real-world applications into a single score. This score will be relative to a baseline implementation, which is currently based on the PULP Platform’s RI5CY 32-bit RISC-V core.
Launched in January by RISC-V pioneer David Patterson and boasting the support of other luminaries including SiFive’s Palmer Dabbelt and Embecosm’s Jeremy Bennet, the team behind the benchmark effort is to present its progress at the RISC-V Zurich workshop this week – and is calling for volunteers to assist with the effort.
“Dhrystone and Coremark have been the de facto standard microcontroller benchmark suites for the last thirty years, but these benchmarks no longer reflect the needs of modern embedded systems,” the team explains. “Embench was explicitly designed to meet the requirements of modern connected embedded systems. The benchmarks are relevant, portable, and well implemented.”
More information is available on the official website.