Category: Community

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

Generic Node Offers Multi-Sensor LoRaWAN Platform at $25 Price Point

A new LoRaWAN sensor platform, dubbed Generic Node, promises to bring low-cost deployment to a wider audience with nine sensors built into a device which is claimed to be available for $25 a unit in medium volume quantities. The LoRaWAN long-range low-power wide area network protocol is at the heart… Read More

“Arm’s Days Could Be Numbered,” Claims RISC-V Vendor

EE Times correspondent Nitin Dahad has pointed to growing troubles for embedded processing giant Arm, and the source should be of no surprise: the growing tide of free and open source silicon (FOSSi) designs, including RISC-V. That the ability to literally clone a GitHub repository and have a fully-working processor… Read More

RIPE NCC’s Marco Hogewoning on IoT Regulation in the UK

Marco Hogewoning, of the RIPE Network Coordination Centre (RIPE NCC), has taken on the topic of regulating the Internet of Things (IoT) in the UK – and highlights that “while there could be benefits […] there are also a lot of challenges.” In a piece penned for Information Age, Marco… Read More

SiFive HiFive1 Board, Courtesy of SiFive

CRU: Wuthering Bytes 2019 Planning, SweRV RISC-V Released, and More

AB Open is pleased to announce a call for participation (CFP) in Wuthering Bytes, the annual community technology festival it produces, seeking those interested in hosting a talk, workshop, roundtable, or other event between Friday the 30th of August and Sunday the 8th of September. Wuthering Bytes — produced by… Read More

Wuthering Bytes Launches 2019 Call for Participation

RISC-V Growth Showcased by Bumper Embedded World 2019 Showing

The free and open-source silicon (FOSSi) ecosystem continues to grow, and nowhere will that growth be more obvious than at the Embedded World 2019 conference this year where 17 companies will be exhibiting RISC-V implementations and supporting technologies alone. Due to take place at the NürnbergMesse, Germany, from Tuesday the… Read More

RISC-V Foundation Announces OpenSBI 0.1 Release

An initial implementation of an open supervisor binary interface (SBI) for RISC-V, imaginatively dubbed OpenSBI v0.1, has been released with support for the HiFive Unleashed, Kendryte K210-based development boards, and QEMU virtual machines. “OpenSBI is an open source implementation of the RISC-V Supervisor Binary Interface (SBI). SBI serves a critical… Read More

Semtech Releases Open-Source LoRaWAN Gateway Software

Semtech has announced the release of an open-source packet-forwarder protocol designed for LoRa-connected gateways, and it has partnered with The Things Industries to integrate it into 700 miniature gateways to be distributed at The Things Conference this weekend. “Semtech’s LoRa Technology is enabling the devices, networks and applications (DNA) of… Read More

Bluetooth 5.1 Standard Adds Centimetre-Scale Location, Direction Finding

The Bluetooth Special Interest Group (SIG) has announced the release of Bluetooth 5.1, which brings with it a new direction-finding feature capable of detecting how far away and in what direction devices are to centimetre-level accuracy. “Location services is one of the fastest growing solution areas for Bluetooth technology, and… Read More

Western Digital Releases SweRV RISC-V Core Source Code

Storage giant Western Digital has officially released the source code for its SweRV RISC-V core, under the permissive Apache 2.0 Licence, allowing anyone to run, experiment with, or modify its implementation. Announced back in December, SweRV is a RISC-V core implementation developed in-house as part of Western Digital’s aim… Read More

CRU: RISC-V’s Bumper Year, LoRaWAN Growth, cocotb 1.1, and More

The RISC-V Foundation has released a video highlighting some of the key features of the 2018 RISC-V Summit, held in Santa Clara late last year and attended by over 1,100 community members. To say that the free and open source silicon (FOSSi) movement in general and RISC-V in particular had… Read More

Cocotb Testbench Hits 1.1, Promises More Rapid Release Schedule

Cocotb, the Coroutine-based Cosimulation TestBench for verifying Verilog or VHDL register-transfer level (RTL) designs using Python, has reached its version 1.1 release – and brings with it the promise of a more rapid and streamlined release schedule for the future. “This release is the culmination of work done by 50… Read More