Category: Community

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

PULP Platform Announces Silicon Labs Partnership

The Parallel Ultra-Low Power (PULP) Platform has announced that Silicon Labs has adopted the platform to extend and customise embedded processor cores in their integrated circuit designs. Now approaching its sixth year, having been launched by Luca Benini at the University of Bologna back in May 2013, the PULP Platform’s… Read More

CRU: Season of Docs, Hardware Compression IP, a SweRV Deep-Dive, and More

Google has announced a new programme, designed to run alongside the Google Summer of Code, through which it aims to improve the quality of documentation in open source projects: the Season of Docs. Google’s Summer of Code (GSoC) is a popular programme through which student developers are partnered with mentor… Read More

Andrew Katz’ Survey of Open Processor Core Licensing Published

Andrew Katz, partner at the law firm Moorcrofts LLP, has published the results of a survey into free and open source silicon (FOSSi) licensing concentrating on processor cores – which includes AB Open’s Andrew Back among its interviewees. Andrew Katz’ report was commissioned by Western Digital, which recently released… Read More

RISC-V Workshop Taiwan Slides Now Available

The RISC-V Foundation has published slides from the RISC-V Workshop Taiwan, which took place earlier this month as a means of showcasing the ecosystem and highlighting both ongoing and future projects. “RISC-V Workshop Taiwan showcased the open, expansive and international RISC-V ecosystem, highlighting current and prospective projects and implementations that… Read More

Microsoft Opens Zipline Hardware-Implementable Compression Algorithm

Microsoft’s cloud computing division, Azure, has announced the release of its hardware-implementable compression algorithm Project Zipline under a permissive licence, as part of the Open Compute project (OCP). “Microsoft’s Project Zipline compression algorithm yields dramatically better results, up to 2X high compression ratios versus the commonly used Zlib-L4 64KB model,”… Read More

Tom Verbeure’s Deep-Dive Into WD’s SweRV RISC-V Core

Tom Verbeure has published comments on a deep-dive of the Western Digital SweRV open-source RISC-V core, following a workshop at the Bay Area RISC-V Meetup earlier this year. Announced late last year and released under a permissive licence in January, the SweRV Core is Western Digital’s open-source implementation… Read More

Calista Redmond Named as RISC-V Foundation CEO

The RISC-V Foundation has announced the appointment of IBM alumnus Calista Redmond as chief executive officer, taking over from interim chief Martin Fink. Calista Redmond’s work history includes 20 years of senior-level management and alliance experience at companies including Affinity Lab and Articulated Impact, including 12 years at IBM where… Read More

Google Announces Season of Docs Open Source Documentation Programme

Linux Foundation to Launch FOSSi-Focused CHIPS Alliance

The Linux Foundation has launched a new group, dubbed the CHIPS Alliance, through which it hopes to support the burgeoning free and open source silicon (FOSSi) ecosystem. Officially announced today by the Linux Foundation, the CHIPS Alliance includes as founding members Esperanto, SiFive, and Western Digital – all of whom… Read More

Seeed Studio MAIX-1 Raspberry Pi AI Hat Layout

Seeed Details RISC-V Raspberry Pi AI HAT, Development Board

Seeed Studio has announced a new Grove AI HAT for the Raspberry Pi, designed for edge computing projects, based around the Sipeed MAIX-I 64-bit RISC-V system-on-module (SOM) – and, interestingly, it will also function as a standalone development board. Unveiled on the official Seeed forum by Elaine Wu, the new… Read More

CRU: Amazon, Imagination Bet on RISC-V, Google Targets Edge Acceleration, and More

Amazon has announced that it has added support for the RISC-V open instruction set architecture (ISA) to the MIT-licensed FreeRTOS real-time operating system kernel. “RISC-V is a free and open ISA that was designed to be simple, extensible, and easy to implement. The simplicity of the RISC-V model, coupled with… Read More

Google Launches Coral Edge TPU Development Board, USB Accelerator

Google has announced it is bringing its Tensor Processing Unit (TPU) technology to external developers for the first time, launching a suite of development boards and accelerators for edge-processing under the Coral brand. Google first announced the Tensor Processing Unit, an in-house custom silicon project to accelerate deep-learning compute performance… Read More