Tom Verbeure has published comments on a deep-dive of the Western Digital SweRV open-source RISC-V core, following a workshop at the Bay Area RISC-V Meetup earlier this year.
Announced late last year and released under a permissive licence in January, the SweRV Core is Western Digital’s open-source implementation of the RISC-V instruction set architecture (ISA). It was also the subject of a deep-dive workshop at the Bay Area RISC-V Meetup, and it’s details from this workshop on which Tom has offered commentary.
“Zvonimir Bandic, Senior Director of Next Generation Platform Technologies Department at Western Digital, gave an excellent presentation, well paced, with sufficient detail to pique my interest to dive deeper in the specifics of the core,” Tom writes. “I’ll go through the presentation and add some extra details that I noted down at the meetup or that were gathered while going through the SweRV source code on GitHub or while going through the RISC-V SweRV EH1 Programmer’s Reference Manual.”
Following a detailed look at the core, based primarily on Zvonimir’s presentation, Tom concludes that while the SweRV Core achieves remarkable performance as measured by CoreMark “it’s clear that SweRV is not a good fit to stick in an FPGA for hobby projects” for a range of reasons: inefficient resource usage on FPGA implementations, poor maximum clockspeed outside ASIC implementations, a lack of support for open-source FPGA toolchains, and that the core wold “probably fill up 50% of a relatively large Artix 7 FPGA, though that needs to be tested in practice.”
Tom’s full write-up is available on his GitHub blog.