Google has announced a new programme, designed to run alongside the Google Summer of Code, through which it aims to improve the quality of documentation in open source projects: the Season of Docs.

Google’s Summer of Code (GSoC) is a popular programme through which student developers are partnered with mentor organisations and financially supported in working on collaborating with a variety of open-source projects through programming. The Season of Docs is, as the name suggests, focused less on programming and more on documentation – an area which too many open source projects let fall by the wayside in their eagerness to focus on the code.

“Season of Docs brings technical writers and open source projects together for a few months to work on open source documentation,” Google’s Sarah Maddox and Andrew Chen explain in the programme’s announcement, which echoes the Summer of Code in offering a financial stipend to participants. “During Season of Docs, technical writers will spend a few months working closely with open source communities. Each writer works with their chosen open source project. The writers bring their expertise to the projects’ documentation while at the same time learning about open source and new technologies.

“Mentors from participating open source organisations share knowledge of their communities’ processes and tools. Together the technical writers and mentors build a new doc set, improve the structure of the existing docs, develop a much-needed tutorial, or improve contribution processes and guides.”

Full details on the new programme, organisation applications for which close in late April and writer applications in late June, are available on the official website.

The Linux Foundation has launched a new group, dubbed the CHIPS Alliance, through which it hopes to support the burgeoning free and open source silicon (FOSSi) ecosystem.

Officially announced today by the Linux Foundation, the CHIPS Alliance includes as founding members Esperanto, SiFive, and Western Digital – all of whom have announced or shipped products based around the open RISC-V instruction set architecture (ISA) – alongside cloud and consumer computing giant Google.

“Open collaboration has repeatedly proven to help industries accelerate time to market, achieve long-term maintainability, and create de facto standards,” explains the Linux Foundation’s Mike Dolan. “The same collaboration model applies to the hardware in a system, just as it does to software components. We are eager to host the CHIPS Alliance and invite more organisations to join the initiative to help propel collaborative innovation within the CPU and SoC markets.”

“As new workloads surface every day, we need new silicon designs in order to optimise processing requirements,” adds Martin Fink, interim chief executive of the RISC-V Foundation and executive vice president and chief technical officer of Western Digital. “Today’s legacy general-purpose architectures are, in some cases, decades old.  With the creation of the CHIPS Alliance, we are expecting to fast-track silicon innovation through the open source community.”

The CHIPS Alliance joins an ecosystem which is defined by its collaborative efforts, from the work of the Free and Open Source Silicon (FOSSi) Foundation and the LibreCores project to events including ORConf and the regular RISC-V Workshops, and it will be exciting to see how the CHIPS Alliance fits into the community as it gets underway.

More information is available from the official website.

Andrew Katz, partner at the law firm Moorcrofts LLP, has published the results of a survey into free and open source silicon (FOSSi) licensing concentrating on processor cores – which includes AB Open’s Andrew Back among its interviewees.

Andrew Katz’ report was commissioned by Western Digital, which recently released its own RISC-V based SweRV Core under a permissive licence, in early 2018; the version published this month in the journal International Free and Open Source Software Law Review represents an edited version for public use. As well as AB Open’s Andrew Back, industry experts interviewed for the report include Krste Asanovic, Julius Baxter, Dr. Jeremy Bennett, Alex Bradbury, David May, Simon Phipps, and Dr. Davide Rossi.

“All interviewees believed that the most commercially effective open hardware core designs were those which adopted permissive licences,” Andrew’s report explains. “The prevalence of these licences is borne out by desktop research. The stated various reasons for this are: that the currently available copyleft open hardware licences are insufficiently clear in their effect to be safely used; that the potential benefits of copyleft licensing in core designs are not yet sufficiently clear to show an overwhelming need to shift to a copyleft model; that copyleft licensing is certainly interesting and may have a place as the market matures. No interviewee was against copyleft core licensing in principle (although there was consensus that a weak copyleft with clearly defined boundaries was more likely to be commercially successful).”

One particularly interesting aspect of the report is the universal popularity of the open RISC-V instruction set architecture (ISA). “Note that even though the interviewees selected were intended to represent a cross section of the core-developing communities, RISC-V was referred to by every interviewee. The emphasis on permissive licensing may therefore be an artefact of the relatively small sample size and a shared familiarity by the interviewees with RISC-V. It may, on the other hand, reflect a reality that RISC-V is the most prominent and widely adopted open ISA currently in use.”

The full report is available to read now in International Free and Open Source Software Law Review Volume 10.

Microsoft’s cloud computing division, Azure, has announced the release of its hardware-implementable compression algorithm Project Zipline under a permissive licence, as part of the Open Compute project (OCP).

“Microsoft’s Project Zipline compression algorithm yields dramatically better results, up to 2X high compression ratios versus the commonly used Zlib-L4 64KB model,” claims Microsoft’s Kushagra Vaid. “Enhancements like this can lead to direct customer benefits in the potential for cost savings, for instance, and indirectly, access to petabytes or exabytes of capacity in a cost-effective way could enable new scenarios for our customers.

“We are open sourcing Project Zipline compression algorithms, hardware design specifications, and Verilog source code for register transfer language (RTL) with initial content available today and more coming soon. This contribution will provide collateral for integration into a variety of silicon components (e.g. edge devices, networking, offload accelerators etc.) across the industry for this new high-performance compression standard.

“Contributing RTL at this level of detail as open source to OCP is industry leading,” Vaid boasts. “It sets a new precedent for driving frictionless collaboration in the OCP ecosystem for new technologies and opening the doors for hardware innovation at the silicon level. Over time, we anticipate Project Zipline compression technology will make its way into several market segments and usage models such as network data processing, smart SSDs, archival systems, cloud appliances, general purpose microprocessor, IoT, and edge devices.”

Project Zipline is available now under the permissive MIT licence via the Open Compute Project GitHub repository.

The RISC-V Foundation has announced the appointment of IBM alumnus Calista Redmond as chief executive officer, taking over from interim chief Martin Fink.

Calista Redmond’s work history includes 20 years of senior-level management and alliance experience at companies including Affinity Lab and Articulated Impact, including 12 years at IBM where she was most recently the vice president of the IBM Z Ecosystem division and, prior to that, the president of the OpenPOWER Foundation.

“I’ve always understood the potential short- and long-term impact of the RISC-V licence-free ISA on the open source community. Having spent a lot of my career working in the open source ecosystem, I’m excited to help RISC-V grow and deliver on the Foundation’s mission of paving the way for the next 50 years of computing design and innovation,” Redmond says of her new role. “From its inception in 2015 until now, the RISC-V Foundation has grown tremendously. I’m ready to leverage that momentum to expand the already impressive RISC-V ecosystem.”

“The RISC-V Foundation Board of Directors is delighted with the appointment of Calista Redmond as our new CEO,” adds Martin Fink. “We envision a seamless transition as Calista leverages her wealth of expertise and experience leading IBM Systems’ strategic business models and open source initiatives. Calista’s accomplishments in advancing IBM Systems, specifically the IBM Z Ecosystem, will be indispensable as the RISC-V Foundation is laser-focused on momentum and growth for 2019 and beyond.”

The appointment comes shortly after the RISC-V Foundation announced it had doubled its members over the last year, with Fink showcasing the figures as proof that “we’ve reached a critical mass of companies adopting RISC-V and actively contributing to the ecosystem.”

Tom Verbeure has published comments on a deep-dive of the Western Digital SweRV open-source RISC-V core, following a workshop at the Bay Area RISC-V Meetup earlier this year.

Announced late last year and released under a permissive licence in January, the SweRV Core is Western Digital’s open-source implementation of the RISC-V instruction set architecture (ISA). It was also the subject of a deep-dive workshop at the Bay Area RISC-V Meetup, and it’s details from this workshop on which Tom has offered commentary.

“Zvonimir Bandic, Senior Director of Next Generation Platform Technologies Department at Western Digital, gave an excellent presentation, well paced, with sufficient detail to pique my interest to dive deeper in the specifics of the core,” Tom writes. “I’ll go through the presentation and add some extra details that I noted down at the meetup or that were gathered while going through the SweRV source code on GitHub or while going through the RISC-V SweRV EH1 Programmer’s Reference Manual.”

Following a detailed look at the core, based primarily on Zvonimir’s presentation, Tom concludes that while the SweRV Core achieves remarkable performance as measured by CoreMark “it’s clear that SweRV is not a good fit to stick in an FPGA for hobby projects” for a range of reasons: inefficient resource usage on FPGA implementations, poor maximum clockspeed outside ASIC implementations, a lack of support for open-source FPGA toolchains, and that the core wold “probably fill up 50% of a relatively large Artix 7 FPGA, though that needs to be tested in practice.”

Tom’s full write-up is available on his GitHub blog.

Seeed Studio has announced a new Grove AI HAT for the Raspberry Pi, designed for edge computing projects, based around the Sipeed MAIX-I 64-bit RISC-V system-on-module (SOM) – and, interestingly, it will also function as a standalone development board.

Unveiled on the official Seeed forum by Elaine Wu, the new design uses the full-size Hardware Attached on Top (HAT) form factor to connect to a Raspberry Pi single-board computer via its 40-pin GPIO header. Its primary feature: a Sipeed MAIX-1 system-on-module, available with or without Wi-Fi connectivity, which gives the Pi access to a 64-bit RISC-V implementation designed to accelerate deep learning workloads at the edge.

The board’s design also includes Grove-format connectors for digital IO, pulse-width modulated (PWM) IO, analogue IO, UART, and I²C, alongside camera connectivity. While the board is primarily designed to be used as a co-processor on top of an Arm-based Raspberry Pi, Wu has confirmed that it will also function as a standalone development board powered via a USB Type-C connector at the bottom left of the PCB.

“The Sipeed MAIX-I module is the first RISC-V 64 AI module based on the powerful KPU K210,” explains Wu. “As a close partner of Sipeed, we are very excited to announce that we are going to make a Grove HAT for Raspberry Pi based on the Sipeed MAIX-I module, aiming at enabling more possibilities of AI model in areas such as predictive maintenance, anomaly detection, robotics and many more. We are going to release two versions, one based on the Sipeed MAIX-I with WiFi and another without. Both can work as a Raspberry Pi HAT, or work by themselves.”

Wu and the team at Seeed are seeking feedback on the design on the company forum. No release date has yet been provided.

Finally, the RISC-V Foundation has published slides from the RISC-V Workshop Taiwan, which took place earlier this month as a means of showcasing the ecosystem and highlighting both ongoing and future projects.

“RISC-V Workshop Taiwan showcased the open, expansive and international RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution of the RISC-V instruction set architecture (ISA),” the Foundation’s summary of the event explains, “with a focus on the growth of the RISC-V ecosystem across China and Asia.

“The event featured a variety of speaking sessions, along with poster presentations and demonstrations. RISC-V Foundation member companies presenting at the Workshop included: Andes Technology; Codasip; Cryptape Technology; Hex Five Security; MediaTek; Microsemi, a wholly owned subsidiary of Microchip Technology Inc.; Nuclei System Technology; SiFive; Software Hardware Consulting (SH Consulting); Syntacore; and Western Digital.”

Slides from all but one session – Ted Speers’ talk, Securing a New Golden Age of Computer Architecture – are available to download now from the RISC-V Foundation website.