Author: Gareth Halfacree

Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.

Dragino LoRaST Adds LoRaWAN Support to NGFF Devices

Devices with M.2 Next-Generation Form Factor (NGFF) slots, typically used for storage devices, can now become LoRaWAN clients thanks to an open-source add-on board from China’s Dragino: The LoRaST. Designed to fit into the M.2 NGFF slots on modern desktop, laptop, and embedded systems, the Dragino LoRaST is based on… Read More

SiFive HiFive1 Board, Courtesy of SiFive

CRU: RISC-V SSDs, Open Satellite Radio, LoRaWAN 1.0.3, and More

This fortnight has been a strong one for the open RISC-V instruction set architecture, starting with the news that IIT Madras has partnered with Intel and HCL Technologies to create an I/O-packed microcontroller test chip in 22nm FinFET that takes aim at ARM Cortex A35/A55 and has successfully booted Linux… Read More

Mobiveil Partners with SiFive for RISC-V-based Programmable Storage

SiFive’s implementation of the open RISC-V instruction set architecture (ISA) has scored another design win, this time to power a smart reprogrammable storage device aimed at the data centre and enterprise markets from Mobiveil. Fresh from the announcement of the world’s first RISC-V based SSD controller and SSD implementation… Read More

Planet Labs Launches OpenLST Satellite Radio Platform

Satellite imaging specialist Planet Labs has announced the launch of OpenLST, an open hardware satellite radio platform for communication with remote vehicles, instruments, and stations using low-cost commercial-off-the-shelf (COTS) components. “Radio system design is often viewed as a ‘black box’ that is out of reach to all but the most… Read More

Fadu Announces World’s First RISC-V SSD, Controller

Fadu, a fabless semiconductor company specialising in the memory and storage markets, has announced the launch of the world’s first RISC-V based solid state drive (SSD) controller, the Annapurna, based on SiFive’s E51 multi-core IP. Beating Western Digital, which announced its own plans to switch from proprietary instruction set architectures… Read More

Disclose.io Aims to Protect Security Researchers

A group of developers, lawyers, and security researchers have joined forces to launch disclose.io, an effort to produce a standardised framework for security disclosures which provide protections for good-faith researchers and the companies whose products they analyse. The field of security research can be a lucrative one: many companies offers… Read More

LoRa Alliance Releases LoRaWAN 1.0.3 Specification

The LoRa Alliance has announced an update to the LoRaWAN 1.0.3 specification for low-power wide-area wireless networks, adding unicast and multicast support to Class B devices and new time synchronisation features for other classes. In its latest update to the open LoRaWAN low-power wide-area network standard, proving popular globally for… Read More

China’s Tencent Joins LoRa Alliance, Plans Shenzhen LoRaWAN Launch

Chinese technology giant Tencent has announced its membership of the LoRa Alliance, as part of a plan to launch a LoRaWAN-based Internet of Things (IoT) network in the bustling city of Shenzhen. “It is clear that LPWANs [low-power wide area networks] are essential for IoT technology and applications, and the… Read More

Silicon Dreams: RISC-V from Emulation to FPGA to ASIC

When working with brand-new silicon designs, particularly free and open source silicon, there’s a bit of a bootstrapping issue: you want to write software for the new silicon, but there’s no silicon yet available; nobody wants to go to the expense of making the silicon, meanwhile, when there’s no software… Read More

CRU: ORConf 2018, Quantum Education, KiCad 5.0, and More

An initial programme for ORConf 2018, the open-source digital design conference to be held in Gdansk, Poland this September, has been published – and there are some big names showing off the state of the art on the schedule. While there are more speakers yet to be announced, the initial… Read More

Google Announces Edge TPU Deep-Learning Accelerator Hardware

Google has announced plans to release a hardware product, dubbed Edge TPU, to bring its TensorFlow-accelerating Tensor Processing Unit (TPU) technology to the Internet of Things. Originally announced back in May 2016 as an internal project to accelerate the company’s search, translation, and other services, the Tensor Processing Unit is… Read More

RISC-V Foundation’s SSC Calls on Big Data, Defence Companies

RISC-V Foundation director Ted Speers has offered up more details on the organisations he would like to see involved in the recently-announced Security Standing Committee. Announced earlier this month by executive director Rick O’Connor, the RISC-V Foundation’s Security Standing Committee came with a request: “[A] call to action for… Read More