Tag: OSHW

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

CRU: LMS8001 Companion, Security Alerts, 14nm RISC-V, and More

The LimeSDR open-source software defined radio (SDR) project has received a boost, quite literally, in the form of the frequency-extending LMS8001 Companion Board, announced as part of the LimeSDR Mini crowdfunding campaign. Built around a Lime Microsystems LMS8001 frequency shifter chip, the Companion Board allows any LimeSDR module –… Read More

CRU: RISC-V Growth, Job Vacancies, and More

Cambridge-based semiconductor specialist UltraSoC has announced its expansion into Bristol, and it’s giving credit for its recent growth to an explosion of interest in the open-source RISC-V instruction set architecture (ISA). “There’s a perfect storm of factors revolutionising the technology business from top to bottom,” says Rupert Baines, UltraSoC’s… Read More

OSDDI: lowRISC, Alex Bradbury

lowRISC is a fantastic initiative to build a fully open source, Linux-capable, 64-bit RISC-V based system-on-chip. Not only this, but a SoC design with additional interesting features such as programmable I/O — think along the lines of XMOS devices — and tagged memory. Read More

OSDDI: OpenRISC, Olof Kindgren

The OpenRISC processor has been around for a good number of years and it has found use in a NASA satellite and Samsung digital televisions, to name just two applications. In this instalment of Open Source Digital Design Insights, long time OpenRISC contributor and open source developer, Olof Kindgren, provides… Read More

OSDDI: SHAKTI Processor, IIT Madras

This latest instalment of Open Source Digital Design Insights is once again from interviews filmed back at ORConf 2015 in Geneva, and this time on the RISC-V based SHAKTI processor from IIT Madras. A project that aims to build 6 processor variants that range from microcontroller up to… Read More

Open Source Digital Design Insights Interview with Javier Serrano, CERN

For the second video in the OSDDI series we have an interview with Javier Serrano, leader of the hardware and timing group at CERN, and a driving force behind many of their open source hardware initiatives. Read More

CRU: RISC-V Calls for Papers, Industrial Hardware, Equipment Hacking, and More

Calls for papers have gone out for the 7th RISC-V Workshop and the first Workshop on Computer Architecture Research with RISC-V (CARRV), both to be held in the US later this year. The 7th RISC-V Workshop, its organisers have confirmed, is to take place on the 28th to the 30th… Read More

Community Round-Up: RISC-V Progress, Amazon Greengrass, Wuthering Bytes and More

Developer Palmer Dabbelt has submitted a RISC-V port of glibc, the GNU C Library, for upstream inclusion and is actively working with others on a patch set for the Linux kernel with a view to mainline acceptance by Linux 4.14. While the open RISC-V instruction set architecture (ISA) has… Read More

Community Round-Up: RISC-V Workshop Proceedings, Open Virtual Platforms, Cortus’ Core, Arduino Cinque, MinnowBoard Turbot, PIC32MZ with GPU, ARM Cortex-A75, Cortex-A55, Intel Compute Cards, Doubling PWM Resolution, and Gordon Williams on Open Source Challenges

The RISC-V Foundation has publicly published the proceedings of the 6th RISC-V Workshop, held early last month in Shanghai, China. Video and, where appropriate, slide decks have been made available from the three public days of the four-day event. Highlights include updates from Rick O’Connor and Yunsup… Read More

Open Source Digital Design Insights launches with Krste Asanović interview

With the groundswell of interest in open source digital design in recent years we decided to take the opportunity to chat with some of the key people involved in this fast growing movement, working in association with the Free and Open Source Silicon Foundation to produce the Open Source… Read More

Community Round-Up: RISC-V Improvements, Caffe2, PCBA Visualisation, Solar Supercapacitors, Arduino Sigfox, Intel Developer Forums, IoT Requirements Guide, and the Vinduino LoRa Project

Researchers at Princeton University have helped boost the robustness of the burgeoning RISC-V architecture, having developed a tool which has picked up on data storage and retrieval ordering problems that could otherwise have derailed attempts to use it in high-reliability applications. “Incorrect memory access orderings can result in software… Read More

Community Round-Up: ARM DynamIQ, GAP8, RISC-V Survey, BeagleBone Blue, Intel tinyTILE, Flow Batteries, Vint Cerf on Security, Employee IP Agreements, and an IoTUK Boost Extension

ARM, now under the ownership of Japanese technology giant Softbank, has announced a new microarchitecture for its next-generation processors, built with many-core and deep-learning projects firmly in mind: DynamIQ. “DynamIQ technology is a monumental shift in multicore microarchitecture for the industry and the foundation for future ARM Cortex-A processors. The… Read More