Tag: FOSSi

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

RISC-V Foundation Announces OpenSBI 0.1 Release

An initial implementation of an open supervisor binary interface (SBI) for RISC-V, imaginatively dubbed OpenSBI v0.1, has been released with support for the HiFive Unleashed, Kendryte K210-based development boards, and QEMU virtual machines. “OpenSBI is an open source implementation of the RISC-V Supervisor Binary Interface (SBI). SBI serves a critical… Read More

Western Digital Releases SweRV RISC-V Core Source Code

Storage giant Western Digital has officially released the source code for its SweRV RISC-V core, under the permissive Apache 2.0 Licence, allowing anyone to run, experiment with, or modify its implementation. Announced back in December, SweRV is a RISC-V core implementation developed in-house as part of Western Digital’s aim… Read More

SiFive HiFive1 Board, Courtesy of SiFive

CRU: RISC-V’s Bumper Year, LoRaWAN Growth, cocotb 1.1, and More

The RISC-V Foundation has released a video highlighting some of the key features of the 2018 RISC-V Summit, held in Santa Clara late last year and attended by over 1,100 community members. To say that the free and open source silicon (FOSSi) movement in general and RISC-V in particular had… Read More

Cocotb Testbench Hits 1.1, Promises More Rapid Release Schedule

Cocotb, the Coroutine-based Cosimulation TestBench for verifying Verilog or VHDL register-transfer level (RTL) designs using Python, has reached its version 1.1 release – and brings with it the promise of a more rapid and streamlined release schedule for the future. “This release is the culmination of work done by 50… Read More

Semiconductor Engineering on RISC-V, FOSSi’s Growing Potential

Semiconductor Engineering’s Brian Bailey has published a piece on the growth of RISC-V, including comment from industry experts including SiFive’s Krste Asanovic and Microsemi’s Ted Speers – and the conclusion that 2019 will be a year of major design wins for the open instruction set architecture. Beginning with a look… Read More

Ground Electronics' SiFive HiFive Unleashed Case

RISC-V Summit 2018 Highlight Video Celebrates a Banner Year

CRU: Raspberry Pi Goes RISC-V, New FOSS Business Model, KiCon 2019, and More

Wave Computing has announced the MIPS Open initiative, under which it plans to make the instruction set architecture (ISA) available free of charge with no licensing or royalty payments required – a clear response to the growing popularity of the open RISC-V ISA. Wave Computing, which acquired MIPS from Imagination… Read More

Design News Picks 2019 as “The Year of Open Source”

Design News’ Chris Wiltz has predicted that 2019 will be “the year of open source,” and while it’s hard to imagine the impact of open source software getting any greater than it already has it’s clear that the impetus behind open hardware is growing at an exponential pace. In the… Read More

Raspberry Pi Foundation Announces RISC-V Foundation Membership

The Raspberry Pi Foundation has announced its membership of the RISC-V Foundation at the Silver Member tier, offering support for the instruction set architecture on a software – though not yet hardware – level. The original Raspberry Pi launched in February 2012 as a low-cost single-board computer (SBC) primarily targeting… Read More

VerilogCreator Tunes QtCreator IDE for FPGA Project Use

Engineers working on field-programmable gate array (FPGA) projects and looking for a friendly development environment to add to their toolchain now have a new option: the VerilogCreator plugin for QtCreator. Written by Rochus Keller and brought to our attention by Hackaday, VerilogCreator is designed to turn the QtCreator integrated… Read More

Thales, IIT Madras Partner for Fault-Tolerant SHAKTI RISC-V Processors

Thales, which recently became a member of the RISC-V Foundation, has announced a joint project with IIT Madras to develop a fault-tolerant version of the SHAKTI Project RISC-V CPU. “After the two successful fabrication and booting of SHAKTI with two technology nodes, 22nm (Intel Fab, Oregon USA) and 180nm… Read More